Abstract: Methods and apparatuses for voltage comparators are described. In one example, a circuit for a voltage comparator includes a first transistor, a second transistor for receiving a first input voltage at a second transistor gate terminal, and a third transistor for receiving a second input voltage at a third transistor gate terminal. The second transistor and the third transistor are connected to the first transistor at a first node. A fourth transistor is connected to the second transistor at a second node, and a fifth transistor is connected to the third transistor at a third node. One or more capacitors are connected between the third node and a fourth node, where the fourth node includes the second transistor gate terminal. One or more capacitors are connected between the second node and a fifth node, where the fifth node includes the third transistor gate terminal. In one example operation, the one or more capacitors provide regenerative gain.

Abstract: Methods and apparatuses for clock signal phase measurement and control are described. In one example, a clock signal phase measurement system includes a reference clock signal line to provide a reference clock signal, a delay line to provide an output clock signal, and a wild clock. The clock signal phase measurement system includes a phase sensor configured to randomly and simultaneously sample the reference clock signal and the output clock signal utilizing the wild clock to obtain a phase data. The phase sensor is further configured to measure from the phase data a phase difference between the reference clock signal and the output clock signal.

Abstract: A system and method are provided for selectively coupled parasitic compensation for voltage offset in an electronic circuit. At least one compensation cell is coupled to an input stage for the circuit. The compensation cell includes an isolation node disposed in spaced manner from control and sampling nodes defined by the input stage. The isolation node is configured to form first and second parasitic capacitances respectively with the control and sampling nodes during system operation. An offset switch is coupled to the isolation node and selectively set between first and second switching states. The offset switch selectively either maintains or interrupts a series coupling of the first and second parasitic capacitances between the control and sampling nodes; and, the sampling node is thereby adaptively adjusted in voltage by a predetermined portion of a control signal applied to the control node.

Abstract: A system and method are provided which incrementally samples and delays a signal passed through a transmission channel thereto. A receiver section is provided with a delay stage including a sample storage portion having a plurality of capacitors. A switch portion selectively switches the capacitors to respectively store incremental samples of the signal received through the channel. A clock source is provided to generate a plurality of periodic clock signals progressively shifted by a predefined clock phase increment. The clock source drives the switch portion to synchronously cycle the capacitors through at least sample and readout modes of operation, which are mutually offset in time by a preselected number of clock phase increments. The received signal is collectively reconstructed from the incremental samples of the capacitors, such that the reconstructed signal is delayed by the preselected number of clock phase increments.

Abstract: In a clock recovery system, a phase detector detects a phase error in an incoming data signal, which it outputs as a differential pair of voltage signals representing positive and negative errors, respectively. A proportional filter generates a proportional offset from the phase error, also as a differential pair of voltage signals. An integral filter generates an integral offset from the proportional offset, using positive and negative voltage controlled oscillators to generate oscillating integral offset signals, and an accumulator to increment or decrement a digital counter for each cycle of the integral offset signals. A first, fractional phase interpolator operating over a ninety-degree range adjusts the phase of an initial clock signal to generate an intermediate clock signal, according to the proportional offset. A second phase interpolator adjusts the phase of the intermediate clock signal to generate an adjusted clock signal, according to the integral offset.

Abstract: A time to digital converter with a successive approximation architecture (300) and a method thereof is provided. The time to digital converter (300) includes successive approximation analog to digital converter circuitry (310) configured for converting the differential voltage established in the digital to analog converter (305) of the successive approximation analog to digital converter circuitry (310) to a digital representation thereof, where the differential voltage corresponds to a measured time period representing a time difference between receipt of leading edges of two signals. Time to digital converter (300) may incorporate a current switching unit (340?) having a plurality of current switching circuits (303a-303n, 304a-304n) arranged in parallel to increase the precision of digital time output of time to digital converter (300). The plurality of current switching circuits (303a-303n, 304a-304n) can be selectively enabled to alter the sensitivity of the time to digital converter (300).

Abstract: A system and method are provided for boosting a selective portion of a drive signal for chip-to-chip transmission across an interconnection interface. The system includes a driver unit generating a drive signal responsive to an input data signal. The drive signal is provided on to at least one output node for transmission through the device interconnection interface, and defines a peak amplitude during a drive period. A boosting unit is coupled to the driver unit for selectively boosting a portion of the drive signal. The boosting unit actuates responsive to the input data signal to selectively apply a boost signal in self-timed manner to the drive signal, so as to thereby augment the drive signal in amplitude over a selected portion of the drive period thereof. In this manner, the boosting unit maintains the peak amplitude of the drive signal at or above a predetermined level throughout the drive period.

Abstract: A system and method are provided for combined generation of I and Q signal references according to a periodic input signal and selective phase interpolation of an output signal with reference thereto. A ring oscillator portion generates an oscillator signal, and includes a plurality of delay stages interconnected in cascade to collectively execute an odd number of signal state inversions within a closed loop. The delay stages establish at respective nodes defined therebetween correspondingly delayed oscillator signal versions, successively shifted in phase by a predetermined phase difference. A signal injection portion selectively applies to at least one node of the ring oscillator portion a current bias according to the periodic input signal, and selectively adjusts each current bias in amplitude. The oscillator signal is thereby frequency locked to the periodic input signal, defining I/Q references with respect to the delayed oscillator signal version established at the current biased node.

Abstract: In one embodiment of the invention, a method is disclosed to generate a clock output signal with selected phase. The method includes selecting a phase delay for the clock output signal; charging a capacitor with a first weighted current during a first phase input clock, charging the capacitor with a second weighted current during a portion of a second phase input clock, and determining if a voltage across the capacitor is greater than or equal to a threshold voltage to generate a first edge of the clock output signal with the selected phase delay. The first weighted current may have a weighting of N out of M to charge the capacitor with a predetermined rate of change in voltage in response to the selected phase delay. The second weighted current may have a weighting of M out of M to charge the capacitor with a constant rate of change.

Abstract: In one embodiment of the invention, a method is disclosed to generate a clock output signal with selected phase. The method includes selecting a phase delay for the clock output signal; charging a capacitor with a first weighted current during a first phase input clock, charging the capacitor with a second weighted current during a portion of a second phase input clock, and determining if a voltage across the capacitor is greater than or equal to a threshold voltage to generate a first edge of the clock output signal with the selected phase delay. The first weighted current may have a weighting of N out of M to charge the capacitor with a predetermined rate of change in voltage in response to the selected phase delay. The second weighted current may have a weighting of M out of M to charge the capacitor with a constant rate of change.

Abstract: A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase difference signal which is a smooth, continuous function of the phase difference between the data signal and the clock signal, such as a phase difference signal which is proportional to the phase difference. The delay lock loop may include two phase shifters in series, and one or both of these may include a phase interpolator.

Abstract: A multiple-input follower amplifier is coupled through a configuration of switching devices to an upper reference voltage at a number of its inputs and to a lower reference voltage at the remaining number of its inputs to form a voltage interpolator. The output of the voltage interpolator is a voltage between the upper and lower reference voltages proportional to the number of inputs coupled to each reference voltage. The voltage interpolator may be constructed so that the interpolated voltage may be selected through a reduced number of signal lines, such as by a row/column selection scheme. A voltage reference circuit providing the upper and lower reference voltages may also implement a row/column selection mechanism, thereby allowing a decoding scheme common to both a voltage reference circuit and a voltage interpolator in a digital-to-analog converter.

Abstract: A self-tuning 3rd order type III phase-locked loop (PLL) is disclosed. In one aspect, the PLL provides frequency control that is implemented in three (3) parallel paths. The PLL provides frequency response tracking using a number of elements including a triple control voltage-controlled oscillator (VCO), a frequency-to-current (F2I) converter, and a switched capacitor loop filter. In addition to compensation for feedback ratio variation, near constant F2I gain over process variations and switched capacitor filters synchronized to a reference signal, near constant VCO gain over process variations allows the open loop frequency response to be tailored to track the reference signal. A high-speed locking technique is employed which significantly reduces acquisition time in low bandwidth cases. This PLL may be fabricated in a 0.18 ?m CMOS logic process.

Abstract: A frequency-to-current converter includes a digitally selectable capacitor, a sampling capacitor, an integrator circuit and an output transconductor. The sampling capacitor is operatively coupled via a first switch to the digitally selectable capacitor. The first switch is operated by a first clock pulse from a clock generator responsive to a reference clock. The integrator circuit has an output operatively coupled via a second switch to the sampling capacitor. The integrator circuit has an output operatively coupled to a control terminal of the transistor. The second switch is operated by a second, non-overlapping clock pulse from the clock generator. A current output by the frequency-to-current converter in response to the continuous question of first and second switches is linearly proportional to the frequency of the reference clock and the capacitance of the digitally selectable capacitor.

Abstract: A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase difference signal which is a smooth, continuous function of the phase difference between the data signal and the clock signal, such as a phase difference signal which is proportional to the phase difference. The delay lock loop may include two phase shifters in series, and one or both of these may include a phase interpolator.

Abstract: A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase difference signal which is a smooth, continuous function of the phase difference between the data signal and the clock signal, such as a phase difference signal which is proportional to the phase difference. The delay lock loop may include two phase shifters in series, and one or both of these may include a phase interpolator.

Abstract: An adaptive phase-locked loop (PLL) circuit produces an output signal having a frequency in reference to the frequency of a reference signal. The PLL circuit includes an oscillator configured to generate the output signal according to a frequency control signal, and a processing circuit configured to generate a feedback signal deriving from the output signal. An adjustable shift circuit is provided to time-shift the feedback signal. The PLL further includes a phase comparison circuit configured to generate a phase error signal indicating a phase error between the time-shifted feedback signal and the reference signal, and a control circuit configured to generate the frequency control signal based on the phase error signal. The adjustable shift circuit adjusts a time-shift amount to time-shift the feedback signal according to the phase error signal.

Abstract: A multiple-input follower amplifier is coupled through a configuration of switching devices to an upper reference voltage at a number of its inputs and to a lower reference voltage at the remaining number of its inputs to form a voltage interpolator. The output of the voltage interpolator is a voltage between the upper and lower reference voltages proportional to the number of inputs coupled to each reference voltage. The voltage interpolator may be constructed so that the interpolated voltage may be selected through a reduced number of signal lines, such as by a row/column selection scheme. A voltage reference circuit providing the upper and lower reference voltages may also implement a row/column selection mechanism, thereby allowing a decoding scheme common to both a voltage reference circuit and a voltage interpolator in a digital-to-analog converter.

Abstract: An adaptive phase-locked loop (PLL) circuit produces an output signal having a frequency in reference to the frequency of a reference signal. The PLL circuit includes an oscillator configured to generate the output signal according to a frequency control signal, and a processing circuit configured to generate a feedback signal deriving from the output signal. An adjustable shift circuit is provided to time-shift the feedback signal. The PLL further includes a phase comparison circuit configured to generate a phase error signal indicating a phase error between the time-shifted feedback signal and the reference signal, and a control circuit configured to generate the frequency control signal based on the phase error signal. The adjustable shift circuit adjusts a time-shift amount to time-shift the feedback signal according to the phase error signal.

Abstract: An auto-zero circuit is disclosed. The auto-zero circuit includes a first set of circuits for implementing a first auto-zero phase and a second set of circuits for implementing a second auto-zero phase. The first set of circuits includes a first differential amplifier and a first feedback path coupled between an output of the first differential amplifier and an input of the first differential amplifier. The second set of circuits includes a second differential amplifier and a second feedback path coupled between an output of the second differential amplifier and an input of the first differential amplifier, where the second feedback path includes an attenuation capacitor for reducing charge injection error and noise error of the auto-zero circuit and a holding capacitor for holding a voltage to be used to correct charge injection error introduced by the first feedback path.