Abstract: A frequency-to-current converter includes a digitally selectable capacitor, a sampling capacitor, an integrator circuit and an output transconductor. The sampling capacitor is operatively coupled via a first switch to the digitally selectable capacitor. The first switch is operated by a first clock pulse from a clock generator responsive to a reference clock. The integrator circuit has an output operatively coupled via a second switch to the sampling capacitor. The integrator circuit has an output operatively coupled to a control terminal of the transistor. The second switch is operated by a second, non-overlapping clock pulse from the clock generator. A current output by the frequency-to-current converter in response to the continuous question of first and second switches is linearly proportional to the frequency of the reference clock and the capacitance of the digitally selectable capacitor.

Abstract: An auto-zero circuit is disclosed. The auto-zero circuit includes a first set of circuits for implementing a first auto-zero phase and a second set of circuits for implementing a second auto-zero phase. The first set of circuits includes a first differential amplifier and a first feedback path coupled between an output of the first differential amplifier and an input of the first differential amplifier. The second set of circuits includes a second differential amplifier and a second feedback path coupled between an output of the second differential amplifier and an input of the first differential amplifier, where the second feedback path includes an attenuation capacitor for reducing charge injection error and noise error of the auto-zero circuit and a holding capacitor for holding a voltage to be used to correct charge injection error introduced by the first feedback path.

Abstract: A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase difference signal which is a smooth, continuous function of the phase difference between the data signal and the clock signal, such as a phase difference signal which is proportional to the phase difference. The delay lock loop may include two phase shifters in series, and one or both of these may include a phase interpolator.

Abstract: A voltage controlled oscillator amplitude control circuit has a voltage controlled oscillator circuit to output an oscillating signal having a controlled amplitude. It also has a control circuit to control the amplitude of the oscillating signal by providing a dominant pole, a filtering function, rectification, and a gain at a single node of the circuit.

Abstract: A digitally tuned and linearized low voltage crystal oscillator integrated circuit requires only an oscillator crystal as external circuitry. The inventive circuit operates at voltages of 3.3V and below and requires no other off-chip components. A crystal oscillator, such as a Pierce crystal oscillator uses an inverting gain stage and a phase shift network composed of an array of switchable capacitors and the crystal. The design offers improvements in power consumption, area, manufacturability and cost.

Abstract: A charge pump having an automatic compensation capability comprises a current source and a current sink. The current source is selectively coupled to the output of the charge pump by a sourcing control. The sourcing control receives an input control signal and responds by controlling the sourcing current flowed from the current source to the output. Likewise, the current sink is selectively coupled to the output of the charge pump by a sinking control. The sinking control receives a second input control signal and responds by controlling the sinking current flowed from the output to the current sink. The charge pump further comprises a sensing circuit and a compensating circuit. The sensing circuit determines whether, given substantially identical input control signals, there is a difference between the sourcing current and the sinking current generated by the charge pump. If so, the sensing circuit provides at its output an indication of the current difference.

Abstract: A voltage to current (V-I) converter includes a low pass filter, a first converting element, a second converting element, and an output. The low pass filter receives an input voltage signal and outputs a filtered voltage signal. The output of the low pass filter is fed to the first converting element, which converts the filtered voltage signal into a corresponding output current which is fed to the output of the V-I converter. Preferably, the voltage to current gain of the first converting element is high. The low pass filter and the first converting element form a low frequency or DC signal path. The V-I converter further includes a second converting element, which receives the input voltage signal and converts it into a corresponding output current which is also fed to the output of the V-I converter. This current is combined with the output current from the first converting element to produce an overall output current.

Abstract: A clock recovery circuit that can be used for recovering a clock signal from a data stream having a high data rate. The clock recovery circuit has a phase interpolator and non-linear digital to analog converters. These circuits are used to interpolate between the phases produced by a voltage controlled oscillator. A determination to advance or hinder a currently selected phase can be made using an up/down detector, a divider, and control logic. The divider can divide not only the up and down pulses produced by the up/down detector, but also the clock frequency. By dividing the clock frequency, the control logic can be designed using CMOS logic circuits.