Patents by Inventor Eric P. Etheridge

Eric P. Etheridge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10476659
    Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digi
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: November 12, 2019
    Assignee: AVNERA CORPORATION
    Inventors: Samuel J. Peters, II, Eric P. Etheridge, Victor Lee Hansen, Alexander C. Stange
  • Publication number: 20190140816
    Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digi
    Type: Application
    Filed: July 30, 2018
    Publication date: May 9, 2019
    Inventors: Samuel J. Peters, II, Eric P. Etheridge, Victor Lee Hansen, Alexander C. Stange
  • Patent number: 10038548
    Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digi
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 31, 2018
    Assignee: AVNERA CORPORATION
    Inventors: Samuel J. Peters, II, Eric P. Etheridge, Victor Lee Hansen, Alexander C. Stange
  • Publication number: 20180054297
    Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digi
    Type: Application
    Filed: October 31, 2017
    Publication date: February 22, 2018
    Inventors: Samuel J. Peters, II, Eric P. Etheridge, Victor Lee Hansen, Alexander C. Stange
  • Patent number: 9832012
    Abstract: A method can include a digital oversampler oversampling an input data stream, a rate generator selecting a frequency that is not less than an expected frequency of the input data stream, a rate generator clock of the rate generator outputting a clock signal that has the selected frequency, determining whether a sample receiver has received at least one sample of the input data stream from the digital oversampler, and, responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler, incrementing a sample counter by each received sample. The method can also include a sample rate converter accumulating samples from the sample receiver at the rate of a “toothless” clock signal, determining whether an output of the sample counter is greater than zero, and, responsive to a determination that the output of the sample counter is greater than zero, an AND gate passing the “toothless” clock signal to the sample rate converter.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: November 28, 2017
    Assignee: AVNERA CORPORATION
    Inventors: Samuel J. Peters, II, Eric P. Etheridge, Victor Lee Hansen, Alexander C. Stange
  • Publication number: 20170222793
    Abstract: A method can include a digital oversampler oversampling an input data stream, a rate generator selecting a frequency that is not less than an expected frequency of the input data stream, a rate generator clock of the rate generator outputting a clock signal that has the selected frequency, determining whether a sample receiver has received at least one sample of the input data stream from the digital oversampler, and, responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler, incrementing a sample counter by each received sample. The method can also include a sample rate converter accumulating samples from the sample receiver at the rate of a “toothless” clock signal, determining whether an output of the sample counter is greater than zero, and, responsive to a determination that the output of the sample counter is greater than zero, an AND gate passing the “toothless” clock signal to the sample rate converter.
    Type: Application
    Filed: April 11, 2017
    Publication date: August 3, 2017
    Inventors: Samuel J. Peters, II, Eric P. Etheridge, Victor Lee Hansen, Alexander C. Stange
  • Patent number: 9621336
    Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated from the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: April 11, 2017
    Assignee: AVNERA CORPORATION
    Inventors: Samuel J. Peters, II, Eric P. Etheridge, Victor Lee Hansen, Alexander C. Stange
  • Patent number: 8848849
    Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 30, 2014
    Assignee: Avnera Corporation
    Inventors: Samuel J. Peters, Eric P. Etheridge, Victor Lee Hanson, Alexander C. Stange
  • Publication number: 20140270028
    Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: Avnera Corporation
    Inventors: Samuel J. Peters, II, Eric P. Etheridge, Victor Lee Hanson, Alexander C. Stange
  • Patent number: 6847905
    Abstract: A method and apparatus for rasterizing a digital sample stream by producing histograms for each of a plurality of time slices forming a display frame. Time slice histograms for at least one display frame are stored in a circular memory buffer and provided to a display raster for display. The first time slice displayed optionally comprises that time slice temporally associated with a trigger condition.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: January 25, 2005
    Assignee: Tektronix, Inc.
    Inventors: Eric P. Etheridge, Kevin T. Ivers, Forrest A. Edwards, Paul M. Gerlach
  • Publication number: 20040008160
    Abstract: A method and apparatus for rasterizing a digital sample stream by producing histograms for each of a plurality of time slices forming a display frame. Time slice histograms for at least one display frame are stored in a circular memory buffer and provided to a display raster for display. The first time slice displayed optionally comprises that time slice temporally associated with a trigger condition.
    Type: Application
    Filed: February 12, 2003
    Publication date: January 15, 2004
    Inventors: Eric P. Etheridge, Kevin T. Ivers, Forrest A. Edwards, Paul M. Gerlach
  • Patent number: 6388595
    Abstract: The subject invention addresses the problem of aliasing in subsampled data by adding dither to the timing of the subsampling of the data. The subject invention solves a speed problem caused by delays in modifying (i.e., dithering) the A/D converter sampling clock. It is herein recognized that to maintain a high acquisition rate one should randomly select (i.e., dither) samples after demultiplexing the data into a wider and slower stream of samples, rather than attempting to modify the high speed A/D converter sampling clock.
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: May 14, 2002
    Assignee: Tektronix, Inc.
    Inventors: Forrest A. Edwards, Eric P. Etheridge
  • Patent number: 6278435
    Abstract: A new oscilloscope design improves the processing of acquired voltage-versus-time data through the efficient high speed acquisition and rasterization of such data into a form that includes multiple-bits-per-pixel intensity information. The multi-bit-per-pixel variable intensity rasterizer is optimized for maximum throughput and most efficient use of memory bandwidth. In the presence of faltering trigger rates, rasterization interruption provides a high probability of capturing the data associated with the slow triggers. Circuitry is provided to compensate for acquisition time and amplitude non-linearities. Many-bits-per-pixel intensity information is mapped into a fewer-bits-per-pixel format by a controllable transfer function that provides multiple viewing capabilities for the operator. Another mode of operation emphasizes infrequent events over commonly occurring ones using variations in brightness or color.
    Type: Grant
    Filed: April 3, 1998
    Date of Patent: August 21, 2001
    Assignee: Tektronix, Inc.
    Inventors: Eric P. Etheridge, Kevin T. Ivers
  • Patent number: 6222521
    Abstract: A new oscilloscope design improves the processing of acquired voltage-versus-time data through the efficient high speed acquisition and rasterization of such data into a form that includes multiple-bits-per-pixel intensity information. The multi-bit-per-pixel variable intensity rasterizer is optimized for maximum throughput and most efficient use of memory bandwidth. In the presence of faltering trigger rates, rasterization interruption provides a high probability of capturing the data associated with the slow triggers. Circuitry is provided to compensate for acquisition time and amplitude non-linearities. Many-bits-per-pixel intensity information is mapped into a fewer-bits-per-pixel format by a controllable transfer function that provides multiple viewing capabilities for the operator. Another mode of operation emphasizes infrequent events over commonly occurring ones using variations in brightness or color.
    Type: Grant
    Filed: April 3, 1998
    Date of Patent: April 24, 2001
    Assignee: Tektronix, Inc.
    Inventors: Kevin T. Ivers, Eric P. Etheridge, Roy I. Siegel, Kayla R. Klingman
  • Patent number: 6219029
    Abstract: A new oscilloscope design improves the processing of acquired voltage-versus-time data through the efficient high speed acquisition and rasterization of such data into a form that includes multiple-bits-per-pixel intensity information. The multi-bit-per-pixel variable intensity rasterizer is optimized for maximum throughput and most efficient use of memory bandwidth. In the presence of faltering trigger rates, rasterization interruption provides a high probability of capturing the data associated with the slow triggers. Circuitry is provided to compensate for acquisition time and amplitude non-linearities. Many-bits-per-pixel intensity information is mapped into a fewer-bits-per-pixel format by a controllable transfer function that provides multiple viewing capabilities for the operator. Another mode of operation emphasizes infrequent events over commonly occurring ones using variations in brightness or color.
    Type: Grant
    Filed: April 3, 1998
    Date of Patent: April 17, 2001
    Assignee: Tektronix, Inc.
    Inventors: Dawn G. Flakne, Eric P. Etheridge, Roy I. Siegel
  • Patent number: 6195080
    Abstract: A new oscilloscope design improves the processing of acquired voltage-versus-time data through the efficient high speed acquisition and rasterization of such data into a form that includes multiple-bits-per-pixel intensity information. The multi-bit-per-pixel variable intensity rasterizer is optimized for maximum throughput and most efficient use of memory bandwidth. In the presence of faltering trigger rates, rasterization interruption provides a high probability of capturing the data associated with the slow triggers. Circuitry is provided to compensate for acquisition time and amplitude non-linearities. Many-bits-per-pixel intensity information is mapped into a fewer-bits-per-pixel format by a controllable transfer function that provides multiple viewing capabilities for the operator. Another mode of operation emphasizes infrequent events over commonly occurring ones using variations in brightness or color.
    Type: Grant
    Filed: April 3, 1998
    Date of Patent: February 27, 2001
    Assignee: Tektronix, Inc.
    Inventor: Eric P. Etheridge
  • Patent number: 6057853
    Abstract: A new oscilloscope design improves the processing of acquired voltage-versus-time data through the efficient high speed acquisition and rasterization of such data into a form that includes multiple-bits-per-pixel intensity information. The multi-bit-per-pixel variable intensity rasterizer is optimized for maximum throughput and most efficient use of memory bandwidth. In the presence of faltering trigger rates, rasterization interruption provides a high probability of capturing the data associated with the slow triggers. Circuitry is provided to compensate for acquisition time and amplitude non-linearities. Many-bits-per-pixel intensity information is mapped into a fewer-bits-per-pixel format by a controllable transfer function that provides multiple viewing capabilities for the operator. Another mode of operation emphasizes infrequent events over commonly occurring ones using variations in brightness or color.
    Type: Grant
    Filed: April 3, 1998
    Date of Patent: May 2, 2000
    Assignee: Tektronix, Inc.
    Inventors: Roy I. Siegel, Eric P. Etheridge, Thuy Nguyen
  • Patent number: 5999163
    Abstract: A method of analyzing and displaying waveforms by acquiring an electrical signal, converting it into a stream of digital data points, and sequentially storing each data point to a memory device. Then, analyzing each of the data points to detect whether the data point is an anomalous data point outside of a preselected range. Until an anomalous data point is detected, the steps of acquiring, converting, storing, and analyzing data are repeated. Shortly after the anomalous data point is detected, storage of the data points to the memory device is stopped, so that the anomalous data point and adjacent data points are preserved in memory. Then, the anomalous data point is displayed, preferably along with the immediately preceding and succeeding data points.
    Type: Grant
    Filed: November 1, 1996
    Date of Patent: December 7, 1999
    Assignee: Tektronix, Inc.
    Inventors: Kevin T. Ivers, Eric P. Etheridge, Roy I. Siegel
  • Patent number: 5986637
    Abstract: To increase the percentage of time that an input signal is actively monitored, a digital oscilloscope has an acquisition system (100) that includes an analog-to-digital converter (15), an acquisition memory (40), an acquisition rasterizer (50), and a raster acquisition memory (60). The rasterizer contains circuitry (52) for concurrently rasterizing and combining the results of several acquisitions together and with a stored composite raster image to produce a new composite raster image, while additional acquisition records are being created and stored in the acquisition memory. A display system 200 takes the composite raster images after they contain the results of many acquisitions and overlays these single-bit raster images on a multi-bit raster image that is then decremented to produce a simulated persistence effect.
    Type: Grant
    Filed: October 17, 1997
    Date of Patent: November 16, 1999
    Assignee: Tektronix, Inc.
    Inventors: Eric P. Etheridge, Gordon W. Shank, Daniel G. Knierim
  • Patent number: 5942927
    Abstract: A first comparison circuit compares an internally generated clock signal with a reference signal and produces a first error signal in response to timing differences between rising edges of the clock signal and the reference signal. A second comparison circuit compares the internally generated clock signal with the reference signal and produces a second error signal in response to timing differences between falling edges of the clock signal and the reference signal. The first and second error signals are applied to control inputs of a phase shifter chain to control delay in each stage to reduce the timing error with respect to each edge.
    Type: Grant
    Filed: December 9, 1997
    Date of Patent: August 24, 1999
    Assignee: Tektronix, Inc.
    Inventors: Eric P. Etheridge, David J. McKinney, Spiro Sassalos, Grigory Kogan