Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digi

Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digi

Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digi

Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digi

Abstract: A method can include a digital oversampler oversampling an input data stream, a rate generator selecting a frequency that is not less than an expected frequency of the input data stream, a rate generator clock of the rate generator outputting a clock signal that has the selected frequency, determining whether a sample receiver has received at least one sample of the input data stream from the digital oversampler, and, responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler, incrementing a sample counter by each received sample. The method can also include a sample rate converter accumulating samples from the sample receiver at the rate of a “toothless” clock signal, determining whether an output of the sample counter is greater than zero, and, responsive to a determination that the output of the sample counter is greater than zero, an AND gate passing the “toothless” clock signal to the sample rate converter.

Abstract: A method can include a digital oversampler oversampling an input data stream, a rate generator selecting a frequency that is not less than an expected frequency of the input data stream, a rate generator clock of the rate generator outputting a clock signal that has the selected frequency, determining whether a sample receiver has received at least one sample of the input data stream from the digital oversampler, and, responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler, incrementing a sample counter by each received sample. The method can also include a sample rate converter accumulating samples from the sample receiver at the rate of a “toothless” clock signal, determining whether an output of the sample counter is greater than zero, and, responsive to a determination that the output of the sample counter is greater than zero, an AND gate passing the “toothless” clock signal to the sample rate converter.

Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated from the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.

Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.

Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.

Abstract: A method and apparatus for rasterizing a digital sample stream by producing histograms for each of a plurality of time slices forming a display frame. Time slice histograms for at least one display frame are stored in a circular memory buffer and provided to a display raster for display. The first time slice displayed optionally comprises that time slice temporally associated with a trigger condition.

Abstract: A method and apparatus for rasterizing a digital sample stream by producing histograms for each of a plurality of time slices forming a display frame. Time slice histograms for at least one display frame are stored in a circular memory buffer and provided to a display raster for display. The first time slice displayed optionally comprises that time slice temporally associated with a trigger condition.

Abstract: The subject invention addresses the problem of aliasing in subsampled data by adding dither to the timing of the subsampling of the data. The subject invention solves a speed problem caused by delays in modifying (i.e., dithering) the A/D converter sampling clock. It is herein recognized that to maintain a high acquisition rate one should randomly select (i.e., dither) samples after demultiplexing the data into a wider and slower stream of samples, rather than attempting to modify the high speed A/D converter sampling clock.

Abstract: A new oscilloscope design improves the processing of acquired voltage-versus-time data through the efficient high speed acquisition and rasterization of such data into a form that includes multiple-bits-per-pixel intensity information. The multi-bit-per-pixel variable intensity rasterizer is optimized for maximum throughput and most efficient use of memory bandwidth. In the presence of faltering trigger rates, rasterization interruption provides a high probability of capturing the data associated with the slow triggers. Circuitry is provided to compensate for acquisition time and amplitude non-linearities. Many-bits-per-pixel intensity information is mapped into a fewer-bits-per-pixel format by a controllable transfer function that provides multiple viewing capabilities for the operator. Another mode of operation emphasizes infrequent events over commonly occurring ones using variations in brightness or color.

Abstract: A new oscilloscope design improves the processing of acquired voltage-versus-time data through the efficient high speed acquisition and rasterization of such data into a form that includes multiple-bits-per-pixel intensity information. The multi-bit-per-pixel variable intensity rasterizer is optimized for maximum throughput and most efficient use of memory bandwidth. In the presence of faltering trigger rates, rasterization interruption provides a high probability of capturing the data associated with the slow triggers. Circuitry is provided to compensate for acquisition time and amplitude non-linearities. Many-bits-per-pixel intensity information is mapped into a fewer-bits-per-pixel format by a controllable transfer function that provides multiple viewing capabilities for the operator. Another mode of operation emphasizes infrequent events over commonly occurring ones using variations in brightness or color.

Abstract: A new oscilloscope design improves the processing of acquired voltage-versus-time data through the efficient high speed acquisition and rasterization of such data into a form that includes multiple-bits-per-pixel intensity information. The multi-bit-per-pixel variable intensity rasterizer is optimized for maximum throughput and most efficient use of memory bandwidth. In the presence of faltering trigger rates, rasterization interruption provides a high probability of capturing the data associated with the slow triggers. Circuitry is provided to compensate for acquisition time and amplitude non-linearities. Many-bits-per-pixel intensity information is mapped into a fewer-bits-per-pixel format by a controllable transfer function that provides multiple viewing capabilities for the operator. Another mode of operation emphasizes infrequent events over commonly occurring ones using variations in brightness or color.

Abstract: A new oscilloscope design improves the processing of acquired voltage-versus-time data through the efficient high speed acquisition and rasterization of such data into a form that includes multiple-bits-per-pixel intensity information. The multi-bit-per-pixel variable intensity rasterizer is optimized for maximum throughput and most efficient use of memory bandwidth. In the presence of faltering trigger rates, rasterization interruption provides a high probability of capturing the data associated with the slow triggers. Circuitry is provided to compensate for acquisition time and amplitude non-linearities. Many-bits-per-pixel intensity information is mapped into a fewer-bits-per-pixel format by a controllable transfer function that provides multiple viewing capabilities for the operator. Another mode of operation emphasizes infrequent events over commonly occurring ones using variations in brightness or color.

Abstract: A new oscilloscope design improves the processing of acquired voltage-versus-time data through the efficient high speed acquisition and rasterization of such data into a form that includes multiple-bits-per-pixel intensity information. The multi-bit-per-pixel variable intensity rasterizer is optimized for maximum throughput and most efficient use of memory bandwidth. In the presence of faltering trigger rates, rasterization interruption provides a high probability of capturing the data associated with the slow triggers. Circuitry is provided to compensate for acquisition time and amplitude non-linearities. Many-bits-per-pixel intensity information is mapped into a fewer-bits-per-pixel format by a controllable transfer function that provides multiple viewing capabilities for the operator. Another mode of operation emphasizes infrequent events over commonly occurring ones using variations in brightness or color.

Abstract: A method of analyzing and displaying waveforms by acquiring an electrical signal, converting it into a stream of digital data points, and sequentially storing each data point to a memory device. Then, analyzing each of the data points to detect whether the data point is an anomalous data point outside of a preselected range. Until an anomalous data point is detected, the steps of acquiring, converting, storing, and analyzing data are repeated. Shortly after the anomalous data point is detected, storage of the data points to the memory device is stopped, so that the anomalous data point and adjacent data points are preserved in memory. Then, the anomalous data point is displayed, preferably along with the immediately preceding and succeeding data points.

Abstract: To increase the percentage of time that an input signal is actively monitored, a digital oscilloscope has an acquisition system (100) that includes an analog-to-digital converter (15), an acquisition memory (40), an acquisition rasterizer (50), and a raster acquisition memory (60). The rasterizer contains circuitry (52) for concurrently rasterizing and combining the results of several acquisitions together and with a stored composite raster image to produce a new composite raster image, while additional acquisition records are being created and stored in the acquisition memory. A display system 200 takes the composite raster images after they contain the results of many acquisitions and overlays these single-bit raster images on a multi-bit raster image that is then decremented to produce a simulated persistence effect.

Abstract: A first comparison circuit compares an internally generated clock signal with a reference signal and produces a first error signal in response to timing differences between rising edges of the clock signal and the reference signal. A second comparison circuit compares the internally generated clock signal with the reference signal and produces a second error signal in response to timing differences between falling edges of the clock signal and the reference signal. The first and second error signals are applied to control inputs of a phase shifter chain to control delay in each stage to reduce the timing error with respect to each edge.