Abstract: To increase the percentage of time that an input signal is actively monitored, a digital oscilloscope has an acquisition system (100) that includes an analog-to-digital converter (15), an acquisition memory (40), an acquisition rasterizer (50), and a raster acquisition memory (60). The rasterizer contains circuitry (52) for concurrently rasterizing and combining the results of several acquisitions together and with a stored composite raster image to produce a new composite raster image, while additional acquisition records are being created and stored in the acquisition memory. A display system (200) takes the composite raster images after they contain the results of many acquisitions and overlays these single-bit raster images on a multi-bit raster image that is then decremented to produce a simulated persistence effect.

Abstract: A multi-channel trigger dejitter technique uses actual digitized samples from a repetitive waveform signal to correct for jitter in a hardware trigger signal. Interpolated samples are calculated between a set of the digitized samples about the hardware trigger signal, and a hardware trigger level is determined from the closest sample in time to the hardware trigger signal. The hardware trigger level is averaged with that determined from prior acquisitions to produce an average trigger level. The closest sample in time to the average trigger level becomes an averaged trigger signal, and the times for all the digitized samples for that acquisition, as well as all simultaneous acquisitions from other input channels, are adjusted according the difference in time between the hardware and averaged trigger signals. Over several acquisition iterations of the repetitive waveform the amount of jitter between acquisitions is decreased.

Abstract: An ECL to CMOS converter having a diferential ECL clock input and an ECL data input is provided. A reference voltage is generated by averaging the level shifted differential ECL clock signals using a voltage divider. This reference voltage and the level shifted ECL data input are compared by a CMOS comparator to provide a CMOS data output. The level shifters, comparators, and the voltage divider are integrated in a standard VLSI CMOS process that enables the resultant integrated circuit to operate from a single supply voltage.

Abstract: An apparatus for generating a CMOS comparator bias voltage for a CMOS comparator includes a dummy comparator having a negative input and a positive input coupled together to receive a common mode reference voltage corresponding to the common mode input voltage of the CMOS comparator. The dummy comparator also includes a bias input and an output. The apparatus for generating a CMOS comparator bias voltage further includes a bias amplifier having a negative input coupled to the output of the dummy comparator, a positive input for receiving a threshold reference voltage corresponding to the input threshold of the next stage driven by the CMOS comparator, and an output coupled to the bias input of said dummy comparator to form a comparator bias voltage.