Patents by Inventor Eric Pourquier

Eric Pourquier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210313497
    Abstract: An optoelectronic device including a first optoelectronic circuit bonded to a second electronic circuit. The second electronic circuit includes conductive pads. The first optoelectronic circuit includes, for each pixel: at least first and second three-dimensional semiconductor elements extending over a first conductive layer and having the same height; first active areas resting on the first semiconductor elements and capable of emitting or receiving a first electromagnetic radiation; second active areas resting on the second semiconductor elements and capable of emitting or receiving a second electromagnetic radiation; and second, third, and fourth conductive layers electrically coupled to the conductive pads, the second, third, and fourth conductive layers being respectively coupled to the first active areas, to the second active areas, and to the first conductive layer.
    Type: Application
    Filed: June 28, 2018
    Publication date: October 7, 2021
    Applicant: Aledia
    Inventor: Eric Pourquier
  • Publication number: 20210265534
    Abstract: There is described an optoelectronic device where each light-emitting diode has a wire-like shape. Spacing walls are formed so that the lateral sidewalls of each light-emitting diode are surrounded by at least one of the spacing walls. Light confinement walls directly cover the lateral sidewalls of the spacing walls by being in contact with the latter. The spacing walls have a convex-shaped outer face. At least one of the spacing walls has, over a lower portion, a thickness that increases when getting away from the substrate. They have, over an upper portion, a thickness that decreases at the level of the upper border of the light-emitting diode when getting away from the substrate. The light confinement walls have an inner face having a concave shape matching with the convex shape and directed towards the light-emitting diode for which it confines the light radiation thereof.
    Type: Application
    Filed: June 19, 2019
    Publication date: August 26, 2021
    Inventors: Olivier JEANNIN, Erwan DORNEL, Eric POURQUIER, Tiphaine DUPONT
  • Publication number: 20210257512
    Abstract: The manufacture of an optoelectronic device includes the formation of light-emitting diodes where each one has a wire form, the formation of spacing walls made of a first dielectric material transparent to the light radiation originating from the diodes. The lateral sidewalls of each diode are surrounded by spacing walls. Light confinement walls are made of a second material adapted to block the light radiation originating from the diodes. The light confinement walls directly cover the lateral sidewalls of the spacing walls by being in contact with the wherein. A thin layer of the second material is deposited so as to directly cover the lateral sidewalls of the spacing walls by being in contact with the wherein and cover the upper border of the light-emitting diodes. The empty spaces delimited between the spacing walls at the level of the areas between the light-emitting diodes are also filled by the thin layer.
    Type: Application
    Filed: June 19, 2019
    Publication date: August 19, 2021
    Inventors: Olivier JEANNIN, Erwan DORNEL, Eric POURQUIER, Tiphaine DUPONT
  • Publication number: 20210234066
    Abstract: A process for producing at least two adjacent regions, each comprising an array of light-emitting wires connected together in a given region by a transparent conductive layer, comprises: producing, on a substrate, a plurality of individual zones for growing wires extending over an area greater than the cumulative area of the two chips; growing wires in the individual growth zones; removing wires from at least one zone forming an initial free area to define the arrays of wires, the initial free area comprising individual growth zones level with the removed wires; and depositing a transparent conductive layer on each array of wires to electrically connect the wires of a given array of wires, each conductive layer being separated from the conductive layer of the neighbouring region by a free area. A device obtained using the process of the invention is also provided.
    Type: Application
    Filed: April 16, 2021
    Publication date: July 29, 2021
    Inventors: Eric POURQUIER, Hubert BONO
  • Patent number: 11063177
    Abstract: A process for producing at least two adjacent regions, each comprising an array of light-emitting wires connected together in a given region by a transparent conductive layer, comprises: producing, on a substrate, a plurality of individual zones for growing wires extending over an area greater than the cumulative area of the two chips; growing wires in the individual growth zones; removing wires from at least one zone forming an initial free area to define the arrays of wires, the initial free area comprising individual growth zones level with the removed wires; and depositing a transparent conductive layer on each array of wires to electrically connect the wires of a given array of wires, each conductive layer being separated from the conductive layer of the neighbouring region by a free area. A device obtained using the process of the invention is also provided.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: July 13, 2021
    Assignees: ALEDIA, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Eric Pourquier, Hubert Bono
  • Patent number: 10797200
    Abstract: The invention relates to a method for manufacturing an optoelectronic device (1), comprising the following steps: a) providing a growth substrate (10) made from a semiconductor material; b) forming a plurality of diodes (20) each comprising a lower face (20i); c) removing at least a portion (12; 13) of the substrate so as to free the lower face (20i); wherein: step a) involves producing a lower part and an upper part of the substrate, the upper part (12) having a uniform thickness (eref) and a level of doping less than that of the lower part; step c) involving removal of the lower part (11) by selective chemical etching with respect to the upper part (12).
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: October 6, 2020
    Assignee: ALEDIA
    Inventor: Eric Pourquier
  • Publication number: 20200161285
    Abstract: An optoelectronic device including: a first circuit including a substrate having first and second opposite faces, the first circuit having display pixels, each display pixel having, on the side of the first face, a first light-emitting diode having a first active region adapted to emit a first radiation and, extending from the second face, a second light-emitting diode having a second active region adapted to emit a second radiation, the surface area, viewed from a direction orthogonal to the first face, of the first active region being at least twice as big as the surface area, viewed from the direction, of the second active region; and a second circuit bonded to the first circuit on the side of the first light-emitting diode and electrically linked to the first and second light-emitting diodes.
    Type: Application
    Filed: June 21, 2018
    Publication date: May 21, 2020
    Applicant: Aledia
    Inventors: Wei Sin Tan, Philippe Gilet, Eric Pourquier, Zine Bouhamri, Pamela Rueda Fonseca
  • Publication number: 20190348566
    Abstract: The invention relates to a method for manufacturing an optoelectronic device (1), comprising the following steps: a) providing a growth substrate (10) made from a semiconductor material; b) forming a plurality of diodes (20) each comprising a lower face (20i); c) removing at least a portion (12; 13) of the substrate so as to free the lower face (20i); wherein: step a) involves producing a lower part and an upper part of the substrate, the upper part (12) having a uniform thickness (eref) and a level of doping less than that of the lower part; step c) involving removal of the lower part (11) by selective chemical etching with respect to the upper part (12).
    Type: Application
    Filed: December 22, 2017
    Publication date: November 14, 2019
    Inventor: Eric Pourquier
  • Publication number: 20190334064
    Abstract: The invention relates to a method for producing an optoelectronic device (1) including a matrix array of light-emitting diodes (4) and a plurality of photoluminescent pads (61, 62, 63 . . . ) that are each located facing at least some of said light-emitting diodes (4), including the following steps: forming said plurality of photoluminescent pads (61, 62, 63 . . . ) by photolithography from at least one photoresist (51, 52, 53 . . . ) containing photoluminescent particles, said photoresist having been deposited beforehand on a supporting surface (3; 3?); forming reflective walls (101, 102, 103 . . . ) covering lateral flanks (81, 82, 83 . . . ) of said photoluminescent pads (61, 62, 63 . . . ) by deposition of at least one thin-layer section (91, 92, 93 . . . ) on the lateral flanks.
    Type: Application
    Filed: December 22, 2017
    Publication date: October 31, 2019
    Inventors: Eric POURQUIER, Philippe GILET, Chang YING-LAN
  • Patent number: 9954141
    Abstract: A process for fabricating an electronic device including a substrate and microwires or nanowires resting on the substrate, the process including successive steps of covering the wires with an insulating layer, covering the insulating layer with an opaque layer, depositing a first photoresist layer over the substrate between the wires, etching the first photoresist layer over a first thickness by photolithography, etching the first photoresist layer remaining after the preceding step over a second thickness by plasma etching, etching the portion of the opaque layer not covered by the first photoresist layer remaining after the preceding step, etching the portion of the insulating layer not covered by the opaque layer, removing the first photoresist layer remaining after the preceding step, and removing the opaque layer.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: April 24, 2018
    Assignees: Aledia, Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Eric Pourquier, Philippe Gibert, Brigitte Martin
  • Publication number: 20180019376
    Abstract: A process for fabricating an electronic device including a substrate and microwires or nanowires resting on the substrate, the process including successive steps of covering the wires with an insulating layer, covering the insulating layer with an opaque layer, depositing a first photoresist layer over the substrate between the wires, etching the first photoresist layer over a first thickness by photolithography, etching the first photoresist layer remaining after the preceding step over a second thickness by plasma etching, etching the portion of the opaque layer not covered by the first photoresist layer remaining after the preceding step, etching the portion of the insulating layer not covered by the opaque layer, removing the first photoresist layer remaining after the preceding step, and removing the opaque layer.
    Type: Application
    Filed: December 24, 2015
    Publication date: January 18, 2018
    Applicants: Aledia, Commissariat à I'Énergie Atomique et aux Énergies Alternatives
    Inventors: Eric Pourquier, Philippe Gibert, Brigitte Martin
  • Publication number: 20150333216
    Abstract: A process for producing at least two adjacent regions, each comprising an array of light-emitting wires connected together in a given region by a transparent conductive layer, comprises: producing, on a substrate, a plurality of individual zones for growing wires extending over an area greater than the cumulative area of the two chips; growing wires in the individual growth zones; removing wires from at least one zone forming an initial free area to define the arrays of wires, the initial free area comprising individual growth zones level with the removed wires; and depositing a transparent conductive layer on each array of wires to electrically connect the wires of a given array of wires, each conductive layer being separated from the conductive layer of the neighbouring region by a free area. A device obtained using the process of the invention is also provided.
    Type: Application
    Filed: December 20, 2013
    Publication date: November 19, 2015
    Inventors: Eric POURQUIER, Hubert BONO
  • Patent number: 8003433
    Abstract: The present application relates to the fabrication of an electronic component. The component comprises two, superposed integrated circuits: one of which is formed on the front side of a thinned first substrate, and the other of which is produced on the front side of a second substrate, with an insulating planarization layer interposed between the front sides of the two substrates. The silicon of the backside of the thinned substrate is opened locally above a first conducting area located in the thinned substrate and above a second conducting area located in the second substrate. A conducting layer portion, deposited on both areas, electrically connects them so as to provide the interconnection between the two circuits. The external connection pads may also be formed in this conducting layer.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: August 23, 2011
    Assignee: E2V Semiconductors
    Inventor: Eric Pourquier
  • Publication number: 20090275165
    Abstract: The invention relates to the fabrication of an electronic component having a very high integration density, notably an image sensor. The component comprises two, superposed integrated circuits, one of which one (the image sensor) is formed on the front side of a thinned first silicon substrate (12) and the other of which is produced on the front side of a second substrate (30), with an insulating planarization layer (28, 48) interposed between the front sides of the two substrates. The silicon (12) of the backside of the thinned substrate is opened locally above a first conducting area (P1) located in the thinned substrate and above a second conducting area (P2) located in the second substrate. A conducting layer portion (50), deposited on both areas, electrically connects them so as to provide the interconnection between the two circuits. The external connection pads (PL1) may also be formed in this conducting layer (50).
    Type: Application
    Filed: December 11, 2007
    Publication date: November 5, 2009
    Inventor: Eric Pourquier
  • Patent number: 7217590
    Abstract: The invention relates to very small-sized color image sensors. The sensor according to the invention is made by the following method: the formation, on the front face of the semiconductive wafer (10), of a series of active zones (ZA) comprising image detection circuits and each corresponding to a respective image sensor, each active zone comprising photosensitive zones (12) covered with conductive and insulating layers (14, 16) enabling the collection of electrical charges generated in the photosensitive zones, the transfer of the wafer (10) by its front face against the front face of a supporting substrate (20), the elimination of the major part of the thickness of the semiconductive wafer, leaving a very fine semiconductive layer (30) on the substrate, this fine semiconductive layer comprising the photosensitive zones, the deposition and etching of color filters (18) on the semiconductive layer thus thinned.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: May 15, 2007
    Assignee: Atmel Grenoble S.A.
    Inventors: Eric Pourquier, Louis Brissot, Gilles Simon, Alain Jutant, Philippe Rommeveaux
  • Patent number: 6972210
    Abstract: The invention relates to the making of color image sensors for miniature cameras. The method of fabrication includes the formation on the front face of a semi-conductive wafer of a series of active zones comprising image detection circuits, each corresponding to a respective image sensor. Each active zone is surrounded by input/output pads. The wafer is transferred by its front fact against the front face of a supporting substrate. The major part of the thickness of the semiconductor wafer is eliminated, leaving a very fine semi-conductive layer including the image detection circuits on the substrate. This method is characterized in that firstly, layers of color filters are deposited and then etched on the semi-conductive layer thus thinned.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: December 6, 2005
    Assignee: Atmel Grenoble S.A.
    Inventors: Eric Pourquier, Philippe Rommeveaux
  • Patent number: 6960483
    Abstract: The invention relates to method for making a color image sensor. The method comprises: the formation, on the front face of a semiconductive wafer (10), of a series of active zones (ZA) comprising image detection circuits and each corresponding to a respective image sensor, each active zone being surrounded by input/output pads (22), the transfer of the wafer by its front face against the front face of a temporary supporting substrate (20), the elimination of the major part of the thickness of the silicon wafer, leaving a fine silicon layer (30) on the substrate, this fine silicon layer comprising the image detection circuits.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: November 1, 2005
    Assignee: Atmel Grenoble S.A.
    Inventor: Eric Pourquier
  • Patent number: 6933585
    Abstract: The invention concerns a color image sensor that can be used to make a miniature camera, and a corresponding method for making this sensor. The image sensor comprises a transparent substrate (40) on the upper part of which are superimposed, successively, a mosaic of color filters (18), a very thin silicon layer (30) comprising photosensitive zones, and a stack of conductive layers (14) and insulating layers (16) defining image detection circuits enabling the collection of the electrical charges generated by the illumination of the photosensitive zones through the transparent substrate. The manufacturing method consists in producing the photosensitive circuits on a silicon wafer, transferring said wafer on to a temporary substrate, thinning the wafer down to a thickness of about three to 30 micrometers, depositing color filters on the surface of the remaining silicon layer and transferring the structure to a permanent transparent substrate and eliminating the temporary substrate.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: August 23, 2005
    Assignee: Atmel Grenoble S.A.
    Inventors: Louis Brissot, Eric Pourquier
  • Publication number: 20050032265
    Abstract: The invention relates to method for making a color image sensor. The method comprises: the formation, on the front face of a semiconductive wafer (10), of a series of active zones (ZA) comprising image detection circuits and each corresponding to a respective image sensor, each active zone being surrounded by input/output pads (22), the transfer of the wafer by its front face against the front face of a temporary supporting substrate (20), the elimination of the major part of the thickness of the silicon wafer, leaving a fine silicon layer (30) on the substrate, this fine silicon layer comprising the image detection circuits.
    Type: Application
    Filed: August 30, 2002
    Publication date: February 10, 2005
    Inventor: Eric Pourquier
  • Publication number: 20040266052
    Abstract: The invention relates to the making of color image sensors for miniature cameras.
    Type: Application
    Filed: February 4, 2004
    Publication date: December 30, 2004
    Inventors: Eric Pourquier, Philippe Rommeveaux