Patents by Inventor Erik Chmelar

Erik Chmelar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11357877
    Abstract: A sterilization enclosure comprises one or more sensors for measuring characteristics within the container during a sterilization process, including one or more characteristics of sterilization agent(s), to determine whether instruments disposed within the container have been exposed to threshold process conditions to ensure a desired level of sterilization for those instruments.
    Type: Grant
    Filed: September 10, 2016
    Date of Patent: June 14, 2022
    Assignee: Stryker Corporation
    Inventors: Bruce Henniges, Robert Childers, Erik Chmelar, Adam Dudycha, Michael Miller, Ali Moaiery, Benjamin John Purrenhage
  • Publication number: 20200237939
    Abstract: A sterilization enclosure comprises one or more sensors for measuring characteristics within the container during a sterilization process, including one or more characteristics of sterilization agent(s), to determine whether instruments disposed within the container have been exposed to threshold process conditions to ensure a desired level of sterilization for those instruments.
    Type: Application
    Filed: September 10, 2016
    Publication date: July 30, 2020
    Applicant: Stryker Corporation
    Inventors: Bruce Henniges, Robert Childers, Erik Chmelar, Adam Dudycha, Michael Miller, Ali Moaiery, Benjamin John Purrenhage
  • Patent number: 8527912
    Abstract: The present invention provides a method for digitally obtaining contours of fabricated polygons. A GDS polygon described in a Geographic Data System (GDS) file is provided. Based on the GDS polygon, a plurality of identical polygons is fabricated with the same fabrication process such that shapes of the plurality of identical polygons are altered by optical effects in the same or similar way. The plurality of identical polygons forms poly-silicon gates of a plurality of test transistors. The position of source and drain islands along a length of a poly-silicon gate for each of the plurality of test transistors is different. Using Automated Test Equipment (ATE), a digital test is performed on a circuit including the plurality of test transistors to obtain test responses, the test responses being raw digital data. The test responses may be displayed in a histogram reflecting a contour of the plurality of identical polygons or post-processed to reconstruct a contour of the plurality of identical polygons.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: September 3, 2013
    Assignee: LSI Corporation
    Inventor: Erik Chmelar
  • Patent number: 8121186
    Abstract: Various embodiments of the present invention provide systems and methods for signal equalization, and in some cases analog to digital conversion. For example, an analog to digital converter is disclosed that includes a comparator bank that receives a reference indicator and is operable to provide a decision output based at least in part on a comparison of an analog input with a reference threshold corresponding to the reference indicator. A range selection filter is included that has a first adjustment calculation circuit and a second adjustment calculation circuit. The first adjustment calculation circuit is operable to calculate a first adjustment feedback value based at least in part on a speculation that the decision output is a first logic level, and the second adjustment calculation circuit is operable to calculate a second adjustment feedback value based at least in part on a speculation that the decision output is a second logic level.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: February 21, 2012
    Assignee: LSI Corporation
    Inventors: Erik Chmelar, Choshu Ito, William Loh
  • Patent number: 7973692
    Abstract: Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a latch based analog to digital converter is disclosed that includes a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: July 5, 2011
    Assignee: LSI Corporation
    Inventors: Erik Chmelar, Choshu Ito, William Loh
  • Patent number: 7956790
    Abstract: Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a retimed analog to digital converter is disclosed that includes a first set of sub-level interleaves and a second set of sub-level interleaves. The first set of sub-level interleaves includes a first sub-level interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase. The second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: June 7, 2011
    Assignee: LSI Corporation
    Inventors: Erik Chmelar, Choshu Ito, William Loh
  • Publication number: 20110016436
    Abstract: The present invention provides a method for digitally obtaining contours of fabricated polygons. A GDS polygon described in a Geographic Data System (GDS) file is provided. Based on the GDS polygon, a plurality of identical polygons is fabricated with the same fabrication process such that shapes of the plurality of identical polygons are altered by optical effects in the same or similar way. The plurality of identical polygons forms poly-silicon gates of a plurality of test transistors. The position of source and drain islands along a length of a poly-silicon gate for each of the plurality of test transistors is different. Using Automated Test Equipment (ATE), a digital test is performed on a circuit including the plurality of test transistors to obtain test responses, the test responses being raw digital data. The test responses may be displayed in a histogram reflecting a contour of the plurality of identical polygons or post-processed to reconstruct a contour of the plurality of identical polygons.
    Type: Application
    Filed: September 24, 2010
    Publication date: January 20, 2011
    Applicant: LSI CORPORATION
    Inventor: Erik Chmelar
  • Patent number: 7827509
    Abstract: The present invention provides a method for digitally obtaining contours of fabricated polygons. A GDS polygon described in a Geographic Data System (GDS) file is provided. Based on the GDS polygon, a plurality of identical polygons is fabricated with the same fabrication process such that shapes of the plurality of identical polygons are altered by optical effects in the same or similar way. The plurality of identical polygons forms poly-silicon gates of a plurality of test transistors. The position of source and drain islands along a length of a poly-silicon gate for each of the plurality of test transistors is different. Using Automated Test Equipment (ATE), a digital test is performed on a circuit including the plurality of test transistors to obtain test responses, the test responses being raw digital data. The test responses may be displayed in a histogram reflecting a contour of the plurality of identical polygons or post-processed to reconstruct a contour of the plurality of identical polygons.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: November 2, 2010
    Assignee: LSI Corporation
    Inventor: Erik Chmelar
  • Patent number: 7779320
    Abstract: An apparatus and method to design an integrated circuit (IC) to reduce the toggling during shifting in and shifting out of test patterns in a IC having scan chains, while maintaining random-like filling of the “don't cares” of a test set. An average pattern of test patterns of a test set is found for both cases of where the test set is fully specified and not fully specified, inverters are judiciously inserted into the scan path and each test pattern is then modified by XOR-ing it with the average test pattern to produce a modified test pattern, which produces less toggling, translating to less power consumption. Further, the random filling of don't cares, as opposed to 0-fill, 1-fill, or adjacent fill, increases defect detection through collateral coverage.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: August 17, 2010
    Assignee: LSI Corporation
    Inventor: Erik Chmelar
  • Publication number: 20100194616
    Abstract: Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a retimed analog to digital converter is disclosed that includes a first set of sub-level interleaves and a second set of sub-level interleaves. The first set of sub-level interleaves includes a first sub-level interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase. The second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase.
    Type: Application
    Filed: June 6, 2008
    Publication date: August 5, 2010
    Inventors: Erik Chmelar, Choshu Ito, William Loh
  • Publication number: 20100195776
    Abstract: Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a latch based analog to digital converter is disclosed that includes a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch.
    Type: Application
    Filed: June 6, 2008
    Publication date: August 5, 2010
    Inventors: Erik Chmelar, Choshu Ito, William Loh
  • Patent number: 7696915
    Abstract: An ADC circuit includes multiple comparators and a controller coupled to the comparators. Each of the comparators is operative to generate an output indicative of a difference between a first signal representative of an input signal applied to the ADC circuit and a corresponding reference signal. The controller is operative to perform at least one of: (i) activating a subset of the comparators during a given sample period being; and (ii) controlling levels of the corresponding reference signals of the comparators as a function of a level of the input signal. A number of active comparators during the given sample period is no greater than one less than a number of regions into which the input signal is quantized.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: April 13, 2010
    Assignee: Agere Systems Inc.
    Inventors: Erik Chmelar, Choshu Ito
  • Patent number: 7656340
    Abstract: Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a pipelined analog to digital converter is disclosed that includes two or more comparators. A first of the comparators is operable to compare an analog input to a first voltage reference upon assertion of the first clock, and a second of the comparators is operable to compare the analog input to a second voltage reference upon assertion of the second clock. The pipelined analog to digital converters further include a multiplexer tree with at least a first tier multiplexer and a second tier multiplexer. The first tier multiplexer receives an output of the first comparator and an output of the second comparator, and the second tier multiplexer receives an output derived from the first tier multiplexer. The second tier multiplexer provides an output bit.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: February 2, 2010
    Assignee: LSI Corporation
    Inventors: Sergey Gribok, Choshu Ito, William Loh, Erik Chmelar
  • Patent number: 7656339
    Abstract: Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, an analog to digital converter is disclosed that includes an analog input that is provided to a comparator bank. The comparator bank receives a reference indicator, and is operable to provide a current output based at least in part on a comparison of the analog input with a reference threshold corresponding to the reference indicator. The analog to digital converter further includes a range selection filter that is operable to receive the current output and to generate the reference indicator based at least in part on a prior output of the comparator bank.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: February 2, 2010
    Assignee: LSI Corporation
    Inventor: Erik Chmelar
  • Publication number: 20090303096
    Abstract: Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, an analog to digital converter is disclosed that includes an analog input that is provided to a comparator bank. The comparator bank receives a reference indicator, and is operable to provide a current output based at least in part on a comparison of the analog input with a reference threshold corresponding to the reference indicator. The analog to digital converter further includes a range selection filter that is operable to receive the current output and to generate the reference indicator based at least in part on a prior output of the comparator bank.
    Type: Application
    Filed: June 6, 2008
    Publication date: December 10, 2009
    Inventor: Erik Chmelar
  • Publication number: 20090304066
    Abstract: Various embodiments of the present invention provide systems and methods for signal equalization, and in some cases analog to digital conversion. For example, an analog to digital converter is disclosed that includes a comparator bank that receives a reference indicator and is operable to provide a decision output based at least in part on a comparison of an analog input with a reference threshold corresponding to the reference indicator. A range selection filter is included that has a first adjustment calculation circuit and a second adjustment calculation circuit. The first adjustment calculation circuit is operable to calculate a first adjustment feedback value based at least in part on a speculation that the decision output is a first logic level, and the second adjustment calculation circuit is operable to calculate a second adjustment feedback value based at least in part on a speculation that the decision output is a second logic level.
    Type: Application
    Filed: June 6, 2008
    Publication date: December 10, 2009
    Inventors: Erik Chmelar, Choshu Ito, William Loh
  • Publication number: 20090303093
    Abstract: Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a pipelined analog to digital converter is disclosed that includes two or more comparators. A first of the comparators is operable to compare an analog input to a first voltage reference upon assertion of the first clock, and a second of the comparators is operable to compare the analog input to a second voltage reference upon assertion of the second clock. The pipelined analog to digital converters further include a multiplexer tree with at least a first tier multiplexer and a second tier multiplexer. The first tier multiplexer receives an output of the first comparator and an output of the second comparator, and the second tier multiplexer receives an output derived from the first tier multiplexer. The second tier multiplexer provides an output bit.
    Type: Application
    Filed: June 6, 2008
    Publication date: December 10, 2009
    Inventors: Sergey Gribok, Choshu Ito, William Loh, Erik Chmelar
  • Publication number: 20090267821
    Abstract: An ADC circuit includes multiple comparators and a controller coupled to the comparators. Each of the comparators is operative to generate an output indicative of a difference between a first signal representative of an input signal applied to the ADC circuit and a corresponding reference signal. The controller is operative to perform at least one of: (i) activating a subset of the comparators during a given sample period being; and (ii) controlling levels of the corresponding reference signals of the comparators as a function of a level of the input signal. A number of active comparators during the given sample period is no greater than one less than a number of regions into which the input signal is quantized.
    Type: Application
    Filed: April 24, 2008
    Publication date: October 29, 2009
    Inventors: Erik Chmelar, Choshu Ito
  • Publication number: 20090217117
    Abstract: An apparatus and method to design an integrated circuit (IC) to reduce the toggling during shifting in and shifting out of test patterns in a IC having scan chains, while maintaining random-like filling of the “don't cares” of a test set. An average pattern of test patterns of a test set is found for both cases of where the test set is fully specified and not fully specified, inverters are judiciously inserted into the scan path and each test pattern is then modified by XOR-ing it with the average test pattern to produce a modified test pattern, which produces less toggling, translating to less power consumption. Further, the random filling of don't cares, as opposed to 0-fill, 1-fill, or adjacent fill, increases defect detection through collateral coverage.
    Type: Application
    Filed: February 21, 2008
    Publication date: August 27, 2009
    Inventor: Erik Chmelar
  • Patent number: 7328386
    Abstract: The invention relates to a method for using checksums in X-tolerant test response compaction in scan-based testing of integrated circuits. Flip-flops of a chip are treated as points of a discrete geometrical structure described in terms of points and lines, with each point representing a MUXed flip-flop holding a value, each line representing a checksum, and each set of parallel lines representing scan chains. The checksums for the flip-flops are calculated along a direction.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: February 5, 2008
    Assignee: LSI Logic Corporation
    Inventors: Mikhail I. Grinchuk, Ahmad A. Alyamani, Erik Chmelar