Abstract: The present invention provides a system and method for implementing postponed quasi-masking test output compression in an integrated circuit. The system includes a compressor for compressing a test response from N scan chains of an integrated circuit into M outputs. The test response may indicate faults in the integrated circuit. M and N are positive integers. The system further includes a correctable multiple input signature register with a size of M, which is communicatively coupled to the compressor. The correctable multiple input signature register is suitable for receiving the M outputs from the compressor as data inputs (s[0], . . . , s[M?1]) and receiving M correction bits (c[0], . . . , c[M?1]) and L address bits (a[0], . . . , a[L?1]) as correction inputs, L being a positive integer, 2L>=M. The correctable multiple input signature register is suitable for detecting faults when there is no or at least one unknown value (i.e., X-value) in the test response.

Abstract: The present invention provides a segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits. A scan chain is divided into a plurality of segments. For a test pattern, compatible segments of the plurality of segments are grouped into compatibility classes. All compatible segments or a subset of them within one of the compatibility classes are simultaneously loaded through selective activation.

Abstract: A compact multipurpose tool including a bit head, a hollow first cylinder that defines a plurality of open-end wrenches on one end, and a second cylinder that communicates with the bit head and can be at least partially housed within the hollow first cylinder. In further features the hollow first cylinder defines a socket on the end opposite the plurality of open-end wrenches and the second cylinder includes a plurality of sockets.

Abstract: The present invention provides a method for digitally obtaining contours of fabricated polygons. A GDS polygon described in a Geographic Data System (GDS) file is provided. Based on the GDS polygon, a plurality of identical polygons is fabricated with the same fabrication process such that shapes of the plurality of identical polygons are altered by optical effects in the same or similar way. The plurality of identical polygons forms poly-silicon gates of a plurality of test transistors. The position of source and drain islands along a length of a poly-silicon gate for each of the plurality of test transistors is different. Using Automated Test Equipment (ATE), a digital test is performed on a circuit including the plurality of test transistors to obtain test responses, the test responses being raw digital data. The test responses may be displayed in a histogram reflecting a contour of the plurality of identical polygons or post-processed to reconstruct a contour of the plurality of identical polygons.

Abstract: Methods for designing and using checksums in X-tolerant test response compaction in scan-based testing of integrated circuits. Flip-flops of a chip are treated as points of a discrete geometrical structure described in terms of points and lines (e.g., a two-dimensional structure, or the like). Each point represents a MUXed flip-flop holding a value. Each line (with points on it) represents a checksum: bit values of flip-flops corresponding to points on the line are all XORed together. A set of all checksums (“lines”) may be separated into subsets, where each subset contains parallel lines. One of these subsets (such that each point belongs to one of lines of the subset) represents scan chains, each line representing one scan chain. In a preferred embodiment, a compactor contains separate parts for each of these subsets such that complexity (the number of gates) of each part depends on the number of scan chains and does not depend on their lengths. Values of checksums may be used as follows.

Abstract: The present invention provides a segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits. A scan chain is divided into a plurality of segments. For a test pattern, compatible segments of the plurality of segments are grouped into compatibility classes. All compatible segments or a subset of them within one of the compatibility classes are simultaneously loaded through selective activation.

Abstract: The present invention provides a system and method for implementing postponed quasi-masking test output compression in an integrated circuit. The system includes a compressor for compressing a test response from N scan chains of an integrated circuit into M outputs. The test response may indicate faults in the integrated circuit. M and N are positive integers. The system further includes a correctable multiple input signature register with a size of M, which is communicatively coupled to the compressor. The correctable multiple input signature register is suitable for receiving the M outputs from the compressor as data inputs (s[0], . . . , s[M?1]) and receiving M correction bits (c[0], . . . , c[M?1]) and L address bits (a[0], . . . , a[L?1]) as correction inputs, L being a positive integer, 2L>=M. The correctable multiple input signature register is suitable for detecting faults when there is no or at least one unknown value (i.e., X-value) in the test response.

Abstract: A truck assembly for a skateboard or the like that is configured to eliminate the undesired ride characteristic of wheel bite without sacrificing the turning responsiveness thereof and without deviating from the general shape and form of a typical skateboard truck. In the preferred embodiment of the invention each truck assembly includes an axle assembly with a ring-shaped member, disposed about a kingpin, that includes two threaded bores longitudinally oriented in the general plane of the ring-shaped member substantially parallel to the axis of the axle and on generally opposite sides of the kingpin, in each of which is positioned a bolt whose distance from the kingpin is determined by actuation of the bolt such that when the axle assembly pivots through an angle about the axis of the kingpin and causes one or more of the bolts to contact the kingpin, the contacting bolt or bolts resists any further pivoting of the axle assembly beyond that angle.

Abstract: A shoelace protector that serves to protect a shoelace at or near the eyelet. The shoelace protector generally comprises a tube with a shaft and a base. The shaft protects the shoelace from damage and the base prevents the tube from being pushed or pulled completely through the eyelet. In the preferred embodiment of the present invention the tube is detachably secured to the shoe by inserting said tube into the eyelet and lacing the shoelace therethrough. In another embodiment of the invention the tube is permanently secured to the eyelet or upper of the shoe.