Abstract: A method to access two memory cells include determining a first cell current flowing through a first memory cell by subtracting a sneak current associated with the first memory cell from a first access current of the first bitline and determining a second cell current flowing through a second memory cell in the first bitline or a second bitline by subtracting the sneak current associated with the first memory cell from a second access current of the first bitline or the second bitline.

Abstract: Encoding or decoding can operate a processing system to apply one or more recursive relations to a known parameter associated with a length m and a Hamming weight l to produce a computed parameter associated with length m?1. An encoding process can thus assign values to bits of a code based on comparison of the data value being encoded and the computed parameter. A decoding process can use the computed parameters in a calculation of a decoded data value.

Abstract: This disclosure provides a circuit that includes a ramp generator to apply a voltage ramp to a resistive memory cell. A sensing circuit can enable the ramp generator and monitor a current output received from the resistive memory cell in response to the applied voltage ramp, wherein the sensing circuit compares the current output to a predetermined current threshold to determine the state of the resistive memory cell.

Abstract: Methods and systems for storing data in memory arrays are described. In one implementation, input bits are encoded into an intermediate binary array having multiple sub-arrays iteratively appended row-wise to the intermediate binary array. First sub-array is generated based on the input bits such that each row of the first sub-array has a number of 1's equal to a fraction of number of columns in the first sub-array, and based on a column balance coding such that the columns of the first sub-array have an equal number of 1's. At least one subsequent sub-array is generated based on a set of bits obtained from balancing termination indices for a previous sub-array and from diagonal bits of the intermediate binary array that are a part of the previous appended sub-array. The intermediate binary array is transformed to an encoded bit pattern. The encoded bit pattern is stored in the memory array.

Abstract: According to an example, in a method for determining a resistance state of a cell in a crossbar memory array, a first read voltage may be applied across a cell to sense a first cell current. In addition, a second read voltage may be applied across the cell to sense a second cell current. A difference value between the first cell current and the second cell current may be identified and a resistance state of the cell may be determined based on the difference value.

Abstract: The present teaching relates to estimating one or more parameters on a system including a plurality of nodes. In one example, the system comprises: one or more learner nodes, each of which is configured for generating information related to a group of words for estimating the one or more parameters associated with a machine learning model; and a plurality of server nodes, each of which is configured for obtaining a plurality of sub-vectors each of which is a portion of a vector that represents a word in the group of words, updating the sub-vectors based at least partially on the information to generate a plurality of updated sub-vectors, and estimating at least one of the one or more parameters associated with the machine learning model based on the plurality of updated sub-vectors.

Abstract: Example implementations disclosed herein can be used to decode memory elements in a crosspoint array. In one example implementation, a drain voltage is applied to a drain terminal of a field effect transistor switch for a selected row in the crosspoint array associated with the selected memory element. A bulk terminal of the field effect transistor switch for the selected row can be biased with a well voltage that is independent of the drain, source, or substrate voltages. In such examples, the gate terminal of the field effect transistor switch for the selected row can be driven with a gate voltage comprising the drain voltage and the well voltage. The drain voltage, the well voltage, and the gate voltage are selected to cause the field effect transistor switch for the selected row to operate as an ohmic switch.

Abstract: A non-volatile memory device with multiple latency tiers includes at least two crossbar memory arrays, each crossbar memory array comprising a number of memory cells, each memory cell connected to a word line and a bit line at a cross point. The crossbar memory arrays each have a different latency. The crossbar memory arrays are formed on a single die.

Abstract: A method to access two memory cells include determining a first cell current flowing through a first memory cell by subtracting a sneak current associated with the first memory cell from a first access current of the first bitline and determining a second cell current flowing through a second memory cell in the first bitline or a second bitline by subtracting the sneak current associated with the first memory cell from a second access current of the first bitline or the second bitline.

Abstract: A device includes a cross-point array and an access circuit to access subsets of memory elements respectively corresponding to encoded blocks of data. For each of the subsets of memory elements, a row or a column of the cross-point array that includes a first memory element in the subset and a second memory element in the subset further includes a third memory element that is between the first and second memory elements along the row or column and is in one of the subsets corresponding to another of the encoded blocks.

Abstract: According to an example, in a method for determining a resistance state of a cell in a crossbar memory array, a first read voltage may be applied across a cell to sense a first cell current. In addition, a second read voltage may be applied across the cell to sense a second cell current. A difference value between the first cell current and the second cell current may be identified and a resistance state of the cell may be determined based on the difference value.

Abstract: This disclosure provides a circuit that includes a ramp generator to apply a voltage ramp to a resistive memory cell. A sensing circuit can enable the ramp generator and monitor a current output received from the resistive memory cell in response to the applied voltage ramp, wherein the sensing circuit compares the current output to a predetermined current threshold to determine the state of the resistive memory cell.

Abstract: According to an example, a method for assigning redundancy in encoding data onto crossbar memory arrays is provided wherein each of said crossbar memory arrays include cells. The data may be allocated to a subset of the cells in multiple crossbar memory arrays. The redundancy for the data may then be assigned based on coordinates of the subset of cells within the multiple crossbar memory arrays onto which the data is allocated.

Abstract: In an example, in a method for encoding data within a crossbar memory array containing cells, bits of input data may be received. The received bits of data may be mapped to the cells in a row of the memory array, in which the cells are to be assigned to one of a low resistance state and a high resistance state. A subset of the mapped bits in the row may be grouped into a word pattern. The word pattern may be arranged such that more low resistance states are mapped to cells that are located closer to a voltage source of the row of the memory array than to cells that are located farther away from the voltage source.

Abstract: Encoding or decoding can operate a processing system to apply one or more recursive relations to a known parameter associated with a length m and a Hamming weight l to produce a computed parameter associated with length m?1. An encoding process can thus assign values to bits of a code based on comparison of the data value being encoded and the computed parameter. A decoding process can use the computed parameters in a calculation of a decoded data value.

Abstract: Bit-flip coding uses a bit-flip encoder to flip bits in a redundancy-intersecting vector of a binary array having n rows and n columns until Hamming weights of the binary array are within a predetermined range ? of n divided by two. Information bits of an input data word to the bit-flip coding apparatus are stored in locations within the binary array that are not occupied by n redundancy bits of a redundancy vector.

Abstract: Methods and systems for storing data in memory arrays are described. In one implementation, input bits are encoded into an intermediate binary array having multiple sub-arrays iteratively appended row-wise to the intermediate binary array. First sub-array is generated based on the input bits such that each row of the first sub-array has a number of 1's equal to a fraction of number of columns in the first sub-array, and based on a column balance coding such that the columns of the first sub-array have an equal number of 1's. At least one subsequent sub-array is generated based on a set of bits obtained from balancing termination indices for a previous sub-array and from diagonal bits of the intermediate binary array that are a part of the previous appended sub-array. The intermediate binary array is transformed to an encoded bit pattern. The encoded bit pattern is stored in the memory array.

Abstract: A memristor memory is disclosed. In an example, the memristor memory comprises a memristor component having a plurality of memristor cells. Each memristor cell is configured to change state based on application of an electric potential. The memristor memory also comprises a controller to read the state of the plurality of memristor cells and identify a subset of the plurality of memristor cells to rewrite. The controller writes the subset of the plurality of memristor cells, and the controller reads an updated state of the plurality of memristor cells to validate the subset was written correctly.

Abstract: A non-volatile memory device with multiple latency tiers includes at least two crossbar memory arrays, each crossbar memory array comprising a number of memory cells, each memory cell connected to a word line and a bit line at a cross point. The crossbar memory arrays each have a different latency. The crossbar memory arrays are formed on a single die.

Abstract: A device includes a cross-point array and an access circuit to access subsets of memory elements respectively corresponding to encoded blocks of data. For each of the subsets of memory elements, a row or a column of the cross-point array that includes a first memory element in the subset and a second memory element in the subset further includes a third memory element that is between the first and second memory elements along the row or column and is in one of the subsets corresponding to another of the encoded blocks.