Patents by Inventor Erik Ordentlich

Erik Ordentlich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160329097
    Abstract: Methods and systems for storing data in memory arrays are described. In one implementation, a data storage system includes a memory array having memory devices in a crossbar configuration, and a memory controller for controlling data storage in the memory array. The memory controller includes an encoder to generate a 2-dimensional encoded bit pattern that encodes the input data. Each run-length of 0's and each run-length of 1's in each row or each column of the encoded bit pattern are at least of a predefined lower limit. The predefined lower limit is at least two. The memory controller includes a write controller to write the encoded bit pattern into the memory devices of the memory array, such that a number of consecutive memory devices in each row or each column of the memory array having a same state is based on the encoded bit pattern.
    Type: Application
    Filed: January 30, 2014
    Publication date: November 10, 2016
    Inventors: Erik Ordentlich, Ron M. Roth
  • Patent number: 9461872
    Abstract: A distinguished node is dynamically selected from a subset of nodes in a wireless network. Data samples from the subset of nodes are received in view of the distinguished node status. At least one estimate is generated from the data samples and the data samples are compressed conditioned on the estimate.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: October 4, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Raul Hernan Etkin, Erik Ordentlich, Gadiel Seroussi, Marcelo Weinberger
  • Patent number: 9405614
    Abstract: One example disclosed in the application is an electronic data-storage device comprising one or more arrays of memory elements. The data-storage device also includes an error-control-coding encoder that encodes received data and a READ/WRITE controller that writes encoded data received from the error-control-coding encoder to a number of memory elements by applying the switching-inducing force or gradient to the one or more arrays of memory elements until more than a maximum-allowed number of WRITE requests have been queued to the WRITE-request buffer, until feedback signals indicate that the WRITE operation has completed, or until the switching-inducing force or gradient has been applied for a maximum application time.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: August 2, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Erik Ordentlich, Gadiel Seroussi
  • Publication number: 20160147598
    Abstract: A method for operating a memory unit is disclosed. The method includes encoding data from a cache line divided in a plurality of groups and generating a plurality of codewords. The method further includes storing the LED data for the cache line combined with the data of the cache line retrieved from a first portion of the codewords across a plurality of chips in the memory unit to create a first tier of protection. The method also includes storing the GEC data for the cache line retrieved from a second portion of the codewords across the plurality of chips to create a second tier of protection for the cache line. The method also includes receiving information corresponding to the first tier of protection, determining whether an error exists in the data of the cache line, decoding the data of the cache line, and outputting the data of the cache line at the controller.
    Type: Application
    Filed: July 31, 2013
    Publication date: May 26, 2016
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Naveen Muralimanohar, Erik Ordentlich
  • Publication number: 20160139988
    Abstract: Operating a memory unit during a memory access operation. The memory unit includes a configuration of N data chips. A line of data stored in the memory unit is divided, with a controller, into a first portion and a second portion. The first portion of the line of data is encoded, with an outer code encoder, to generate an outer code output. The second portion of the line of data and the outer code output from the outer code encoder are encoded, with an inner code encoder, to generate an inner code output. A first layer of protection for the line of data is generated based on the inner code output and is stored to the memory unit, where the first layer of protection includes local error detection (LED) information combined with the line of data. A second layer of protection for the line of data is generated based on the first layer of protection and is stored to the memory unit. A decoding operation to retrieve the line of data is performing at the controller.
    Type: Application
    Filed: July 31, 2013
    Publication date: May 19, 2016
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Naveen Muralimanohar, Erik Ordentlich
  • Patent number: 9142287
    Abstract: A method for encoding bits to be stored within a crossbar memory architecture performed by a physical computing system includes designating, with the physical computing system, a subset of crosspoints within a crossbar matrix, the crossbar matrix comprising a number of disjointed intersecting wire segments, the subset corresponding to a predetermined path through the crossbar matrix; and encoding, with the physical computing system, a number of data bits to be placed along the predetermined path; in which the encoding causes bits pertaining to at least one of the wire segments to be subject to a constraint when the data bits are placed along the predetermined path.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: September 22, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Erik Ordentlich, Ron M. Roth
  • Publication number: 20150248332
    Abstract: According to an example, in a method to manage access to a memory array, a bit string may be encoded with a rank metric code encoder to generate a rank metric codeword having an encoded binary array. The encoded binary array may be modifies so each row of the encoded binary array has at most half of the row with a first bit value and each column of the encoded binary array has at most half of the column with the first bit value. The modified binary array may be stored into corresponding memory devices of the memory array. In addition, the memory array may be read to retrieve a corrupted binary array having a corrupted rank metric codeword and the corrupted rank metric codeword may be decoded with a rank metric code decoder to recover the bit string.
    Type: Application
    Filed: May 14, 2015
    Publication date: September 3, 2015
    Inventors: Erik ORDENTLICH, Ron M. Roth, Gadiel Seroussi
  • Patent number: 9070436
    Abstract: A method is provided to manage access to a memory array. The method includes encoding a bit string with a rank metric encoder to generate an encoded binary array, modifying the encoded binary array so each row has at most half of the row with a bit value and each column has at most half of the column with the bit value, and storing the modified binary array into corresponding memory devices of the memory array.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: June 30, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Erik Ordentlich, Ron M. Roth, Gadiel Seroussi
  • Patent number: 9015405
    Abstract: A method of storing data into a memory array converts an input string into a first binary array with (m?1) rows and (n?1) columns. A second binary array with m rows and n columns in an encoded bit pattern is then generated from the first binary array. The second binary array in the encoded bit pattern has at most n/2 1's in each row and at most m/2 1's in each column, and the m-th row and an n-th column contain information for decoding other entries of the second binary array. The encoded bit pattern of the second binary array is then stored into corresponding memory devices of the memory array.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: April 21, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Erik Ordentlich, Ron M. Roth, Gadiel Seroussi, Pascal Vontobel
  • Patent number: 8949693
    Abstract: Examples of the present invention include an electronic-memory-system component. The electronic-memory-system component includes an array of data-storage elements and an encoder that receives input data, processes the input data as a two-dimensional array of bits by carrying out two passes, in one pass subjecting a portion of each row of the two-dimensional array of bits having more than a threshold weight to a first weight-reduction operation, and, in another pass, subjecting a portion of each considered column of the two-dimensional array of bits having more than a threshold weight to a second weight-reduction operation, one of the first and second weight-reduction operations employing an antipodal mapping and the other of the first and second weight-reduction operations employing bit inversion, generates a codeword corresponding to the input data, and stores the codeword in the array of data-storage elements.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: February 3, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Erik Ordentlich, Ron M. Roth
  • Patent number: 8948524
    Abstract: A joint image compression system and method compress a target image and a reference image under a selected transform to produce a compressed difference image. The joint image compression system includes a computer readable media and a computer program stored on the computer readable media. The computer program includes instructions that implement selecting a transform from among a plurality of transforms that includes a subset determined projective (SDP) transform, where the selected transform minimizes a cumulative mapping error (CME) for corresponding feature points in each of a target image and a reference image. The instructions further implement applying the selected transform to one of the target image and the reference image; forming a difference image under the selected transform and compressing the difference image to produce a compressed difference image.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: February 3, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Cheng Chang, Erik Ordentlich, Krishnamurthy Viswanathan, Marcelo Weinberger
  • Patent number: 8938575
    Abstract: A multi-state memory system with encoding that minimizes half-select currents. The system includes an array of row and column conductors with a plurality of storage cells each capable of being placed into any of three or more physical states. An encoder is connected to receive data bits for storage and to apply activation signals to the row and column conductors to write information to the storage cells. The encoder is programmed to encode the data bits into entries in an array having one row corresponding with each row conductor and one column corresponding with each column conductor; select entries in the array according to half-select currents of the storage cells; apply a predetermined one-dimensional mapping that increases the value of at most one entry in the array to obtain a mapped array; and write entries of the mapped array into the storage cells.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: January 20, 2015
    Assignee: Hewlett-Packard Development Company, L. P.
    Inventors: Erik Ordentlich, Ron M Roth, Gadiel Seroussi
  • Patent number: 8917537
    Abstract: A programmable crossbar array with inline fuses includes a layer of row lines and a layer of column lines with the row lines crossing over the column lines to form junctions and resistive memory elements sandwiched between row lines and a column lines at the junctions. Inline fuses are located in either the row lines, column lines or both. The inline fuses are interposed between the support circuitry and the resistive memory elements. A method for mitigating shorts in a crossbar array is also provided.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: December 23, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Erik Ordentlich, Ron M. Roth, Gadiel Seroussi
  • Patent number: 8902929
    Abstract: An approximate enumerative coding method (100, 200) and apparatus (300) employ a cardinality-approximating (C-A) lower bound in mapping a message M to a 2-dimensional (2-D) codeword array that satisfies a 2-D constraint. The method (100) includes encoding the message M as a codeword array X using an encoder apparatus. The encoding determines entries in a codeword array X using the C-A lower bound. The C-A lower bound is a function of several terms, namely a memory term k, a cardinality of a set of sequences satisfying a horizontal constraint, a columnar extension probability of the 2-D constraint, and a non-negative constant that is a function of the columnar extension probability. The apparatus (300) includes an encoder processor (310), memory (320) and a computer program (330) stored in the memory (320) and executed by the encoder processor (310).
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: December 2, 2014
    Assignee: Hewlett-Packard Developent Company, L.P.
    Inventors: Erik Ordentlich, Ron M. Roth
  • Patent number: 8880782
    Abstract: A data storage system including a memory array including a plurality of memory devices programmable in greater than two states. A memory control module may control operations of the memory array, and an encoder module may encode input data for storing to the memory array. The memory array may be an m×n memory array, and the memory control module may control operations of storing data to and retrieving data from the memory array.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: November 4, 2014
    Assignee: Hewlett Packard Development Company, L. P.
    Inventors: Erik Ordentlich, Ron M. Roth, Gadiel Seroussi
  • Patent number: 8861256
    Abstract: A method of storing data in a memory array with less than half of memory elements in any row and column in a low-resistance state. The data are arranged in a first portion of an encoding array. High-resistance values are entered in a second portion. A codeword is selected from a covering code for each row in which too many entries have low-resistance values. The selected codeword is used to reduce the number of low-resistance values in that row. A codeword is selected for each column in which too many entries have low-resistance values and the codeword is used to reduce the number of such values in that column. The process is repeated until no row and no column has too many low-resistance values. The array entries are stored in corresponding memory elements.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: October 14, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Erik Ordentlich, Ron M Roth
  • Publication number: 20140215121
    Abstract: A method is provided to manage access to a memory array. The method includes encoding a bit string with a rank metric encoder to generate an encoded binary array, modifying the encoded binary array so each row has at most half of the row with a bit value and each column has at most half of the column with the bit value, and storing the modified binary array into corresponding memory devices of the memory array.
    Type: Application
    Filed: January 30, 2013
    Publication date: July 31, 2014
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Erik Ordentlich, Ron M. Roth, Gadiel Seroussi
  • Publication number: 20140211536
    Abstract: A programmable crossbar array with inline fuses includes a layer of row lines and a layer of column lines with the row lines crossing over the column lines to form junctions and resistive memory elements sandwiched between row lines and a column lines at the junctions. Inline fuses are located in either the row lines, column lines or both. The inline fuses are interposed between the support circuitry and the resistive memory elements. A method for mitigating shorts in a crossbar array is also provided.
    Type: Application
    Filed: January 30, 2013
    Publication date: July 31, 2014
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Erik Ordentlich, Ron M. Roth, Gadiel Seroussi
  • Patent number: 8792289
    Abstract: A method for rewriting a memory array with a number of memory elements includes performing a rewrite process to change the memory array from an initial state to a target state in a manner that avoids violating a set of weight constraints at any time during the rewrite process. A memory system includes a memory array and a memory controller configured to perform a rewrite process to change the memory array from an initial state to a target state in a manner that avoids violating a set of weight constraints at any time during the rewrite process.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: July 29, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Erik Ordentlich, Gadiel Seroussi, Pascal Olivier Vontobel
  • Publication number: 20140164869
    Abstract: One example disclosed in the application is an electronic data-storage device comprising one or more arrays of memory elements that each includes a data-storage medium that is switched between two different states by application of a switching-inducing force or gradient to the data-storage medium, a top control element and a bottom control element through which the switching-inducing force or gradient is applied, and a feedback signal. The data-storage device also includes an error-control-coding encoder that encodes received data and a READ/WRITE controller that writes encoded data received from the error-control-coding encoder to a number of memory elements by applying the switching-inducing force to the one or mare arrays of memory elements until feedback signals indicate that the WRITE operation has completed or until the switching-inducing force or gradient has been applied for a maximum application time.
    Type: Application
    Filed: July 27, 2011
    Publication date: June 12, 2014
    Inventors: Erik Ordentlich, Gadiel Seroussi