Abstract: The manufacturing method of a nonvolatile memory and its structure is achieved by building a gate dielectric layer on a base. The gate dielectric contains at least two layers of different material layers. At least one hetero element is planted on the top of the gate dielectric layer so as to increase the electronic trap density. Then rebuild a new top material after removing the upmost layer of material. Finally, build a gate electrode layer on the gate dielectric layer and form source/drain electrodes at the bases of both sides of the gate dielectric layer. In this invention, with the planting of the hetero element, it will form traps in the gate dielectric layer that can catch electrons more easily. Thus, the electrons won't combine together with the increase of operation time. The storage time can be effectively extended and the problem of the combination of bites can be solved.

Abstract: A memory unit comprising a gate electrode, a gate dielectric under said gate electrode, an active area and a metal-semiconductor compound layer is provided. The active area comprises a first source/drain region, a second source/drain region, a normal field channel region formed under said gate electrode, a fringing field channel region formed between said first source/drain region and said normal field channel region, a pocket implantation region formed under the fringing or normal field channel regions and an extension doping region formed between said second source/drain region and said normal field channel region. The metal-semiconductor compound layer is formed over said gate electrode, first source/drain region and second source/drain region.

Abstract: A method for manufacturing a memory unit capable of storing multibits binary information. A gate is formed on a dielectric layer over a semiconductor substrate. Next, a first etching is performed to etch the semiconductor substrate by using the gate acting as an etching mask to remove exposed surface of the dielectric layer. Subsequently, a first oxide layer is conformally formed on the gate and the semiconductor substrate. An charge-trapping layer is conformally formed on the first oxide layer, and subsequently a second oxide layer is conformally formed on the isolating layer. Next, a second etching is performed to etch the second oxide layer and the charging-trapping layer to form sandwich spacers composed of the second oxide layer/the isolating layer/the first oxide layer on the substrate and the gate sidewall.

Abstract: A memory system comprising a memory array having a plurality of memory units, a column decoder, a row decoder, a selecting/driving circuit and a sensing circuit is disclosed. Each memory unit comprises a gate electrode coupled to a word lines, a source region coupled to a source line or a first bit line, a drain region coupled to a drain line or a second bit line, a first spacer between the source region and the gate electrode and a second spacer between the drain region and the gate electrode. When a first-bit program operation is performed on the memory unit, a switch-on signal is applied to the gate, a programming signal is applied to the source region and the drain region is switched to ground. As the memory unit is activated, the carriers are injected and stored in a first spacer, thus represents a first bit in the memory unit.

Abstract: The manufacturing method of a nonvolatile memory and its structure is achieved by building a gate dielectric layer on a base. The gate dielectric contains at least two layers of different material layers. At least one hetero element is planted on the top of the gate dielectric layer so as to increase the electronic trap density. Then rebuild a new top material after removing the upmost layer of4terial. Finally, build a gate electrode layer on the gate dielectric layer and form source/drain electrodes at the bases of both sides of the gate dielectric layer. In this invention, with the planting of the hetero element, it will form traps in the gate dielectric layer that can catch electrons more easily. Thus, the electrons won't combine together with the increase of operation time. The storage time can be effectively extended and the problem of the combination of bites can be solved.

Abstract: The present invention includes a semiconductor layer formed over an insulation layer and a substrate. Doped regions are formed in a portion of the semiconductor layer. A gate dielectric and a gate are respectively formed over the semiconductor layer. The arrangement of the gate sidewall and semiconductor layer surface is substantially orthogonal, multi-portion dielectric layer is formed on the gate and a portion of the silicon layer. Charge trapping dielectrics are attached on the multi-portion dielectric layer acting as carrier trapping structure. The gate-to-source/drain non-overlapped implantation is capable of storing multi-bits per transistor.

Abstract: The present invention discloses a nonvolatile memory with spacer trapping structure, the nonvolatile memory comprising a semiconductor substrate. A gate oxide is formed on the semiconductor substrate. A gate structure is formed on the gate oxide. An isolation layer is formed over the sidewall of the gate structure. First spacers are formed on the sidewall of the isolation layer and becoming the spacer trapping structure for storing carrier. And the p-n junctions of source and drain regions are formed adjacent to the gate structure. Silicide is formed on the gate structure and the source and drain regions.

Abstract: A process for fabricating non-volatile memory by tilt-angle ion implantation comprises essentially the steps of implanting sideling within a nitride dielectric layer heterogeneous elements such as, for example, Ge, Si, N2, O2, and the like, for forming traps capable of capturing more electrons within the nitride dielectric layer such that electrons can be prevented from binding together as the operation time increased; etching off both ends of the original upper and underlying oxide layers to reduce the structural destruction caused by the implantation of heterogeneous elements; and finally, depositing an oxide gate interstitial wall to eradicate electron loss and hence promote the reliability of the device.

Abstract: A memory array including a plurality of word lines, a plurality of first source/drain lines, a plurality of second source/drain lines, and a plurality of memory units. Each memory unit includes a gate electrode coupled to one of the word lines, a first source/drain region coupled to one of the first source/drain lines or first bit lines, a second source/drain region coupled to one of the second source/drain lines or second bit lines, a first spacer between the first source/drain region and the gate electrode to store electrons or electric charges, and a second spacer between the second source/drain region and the gate electrode to store electrons or electric charges.

Abstract: The structure of the nonvolatile memory includes a substrate having source/drain formed at unselected sides and source/drain with extension source/drain formed at other selected sides. A gate dielectric layer is formed on the substrate and a gate is formed on the gate dielectric layer. An isolation layer is formed along the surface of the gate. Spacers are formed attached on the sidewalls of the gate.

Abstract: A nonvolatile memory capable of storing multi-bits binary information is provided. The memory includes an oxide formed on a substrate. A control gate is formed on the oxide. An L-shape structure is attached on sidewall of the control gate. Spacers are formed on the L-shape structure to act as a floating gate. A first doped region and a second doped region is formed in the substrate adjacent to the spacers with a channel between the two doped regions. Wherein the spacer represent a first binary status by injecting and storing electrical charges in the spacers. Or to represent a second binary status by not injecting electrical charges into the spacer.

Abstract: The present invention discloses a nonvolatile memory with undercut trapping structure, the nonvolatile memory comprising a semiconductor substrate. A gate oxide is formed on the semiconductor substrate. A gate structure is formed on the gate oxide, wherein the gate structure including a undercut structure formed at lower portion of the gate structure and inwardly into the gate structure. An isolation layer is formed over the sidewall of the gate structure. First spacers are formed on the sidewall of the isolation layer and filled into the undercut structure for storing carrier and source and drain regions formed adjacent to the gate structure and under the undercut structure. Salicide is formed on the gate structure and the source and drain regions.

Abstract: A nonvolatile memory capable of storing multi-bits binary information is provided. The memory includes an oxide formed on a substrate. A control gate is formed on the oxide. An L-shape structure is attached on sidewall of the control gate. Spacers are formed on the L-shape structure to act as a floating gate. A first doped region and a second doped region is formed in the substrate adjacent to the spacers with a channel between the two doped regions. Wherein the spacer represent a first binary status by injecting and storing electrical charges in the spacers. Or to represent a second binary status by not injecting electrical charges into the spacer.

Abstract: A nonvolatile memory capable of storing multi-bits binary information is provided. The memory includes an oxide formed on a substrate. A control gate is formed on the oxide. An L-shape structure is attached on sidewall of the control gate. Spacers are formed on the L-shape structure to act as a floating gate. A first doped region and a second doped region is formed in the substrate adjacent to the spacers with a channel between the two doped regions. Wherein the spacer represent a first binary status by injecting and storing electrical charges in the spacers. Or to represent a second binary status by not injecting electrical charges into the spacer.

Abstract: The present invention generally relates to provide a fabrication method for forming a flash memory device provided with an adjustable sharp end structure of the floating gate. While the present invention utilizes the dielectric spacer to form the L-shaped floating gate provided with a sharp end structure, the present invention adjust the thickness of the polysilicon layer and the dielectric layer covering on the polysilicon layer surface to adjust the position of the dielectric spacer so as to change the position of the sharp end structure of the L-shaped floating gate and to enhance the ability of erasing control of the flash memory and to simultaneously form a stable and easily controlled channel length and the sharp end structure for point discharging.

Abstract: A nonvolatile memory capable of storing multi-bits binary information is provide. The memory includes an oxide formed on a substrate. A control gate is formed on the oxide. An L-shape structure is attached on sidewall of the control gate. Spacers are formed on the L-shape structure to act as a floating gate. A first doped region and a second doped region is formed in the substrate adjacent to the spacers with a channel between the two doped regions. Wherein the spacers represent a first binary status by injecting and storing electrical charges in the spacers. Or to represent a second binary status by not injecting electrical charges into the spacer.

Abstract: The structure of the FLASH device includes a first dielectric layer formed on a substrate. A floating gate with spacer profile formed on the first dielectric layer. A dielectric spacer is formed on the floating gate for isolation. A second dielectric layer is formed along the approximately vertical surface of the floating gate and the dielectric spacer and a lateral portion of the second dielectric layer laterally extends over the substrate adjacent the floating gate. A control gate is formed on the lateral portion of the second dielectric layer that laterally extends over the substrate. The control gate is formed on the lateral portion of the second dielectric layer.

Abstract: The structure of the FLASH device includes a first dielectric layer formed on a substrate. A floating gate with spacer profile formed on the first dielectric layer. A dielectric spacer is formed on the floating gate for isolation. A second dielectric layer is formed along the approximately vertical surface of the floating gate and the dielectric spacer and a lateral portion of the second dielectric layer laterally extends over the substrate adjacent the floating gate. A control gate is formed on the lateral portion of the second dielectric layer that laterally extends over the substrate. The control gate is formed on the lateral portion of the second dielectric layer.

Abstract: A method for etching a pattern within a silicon containing dielectric layer upon a substrate employed within a microelectronics fabrication, employing a plasma activated reactive gas mixture, with layer material etch rate, etch rate ratio and pattern aspect ratio controlled by controlling the gas composition. There is provided a silicon substrate formed upon it a patterned microelectronics layer over which is formed a silicon containing dielectric layer. There is placed the silicon substrate within a reactor chamber equipped with electrodes which is evacuated. There is then filled the reactor chamber with a reactive gas mixture consisting of an oxidizing gas and two reactive gases. There may be optionally included in the reactive gas mixture nitrogen and inert gases for control purposes, but excluded from the reactive gas mixture are oxidizing gases containing carbon and oxygen.

Abstract: A method for making a novel structure having borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections on integrated circuits is achieved. An etch-stop layer and a planar insulating layer are formed over the devices on a substrate. Contact openings are etched in the insulating layer to the etch-stop layer and the etch-stop layer is removed over the N− contact areas. An N+ doped polysilicon layer is deposited, and second contact openings are etched in the polysilicon and insulating layers over N+ and P+ contacts on the substrate to the etch-stop layer. The etch-stop layer is selectively removed and a conducting barrier layer and a metal layer are deposited having a second etch-stop layer on the surface. The layers are patterned to form interconnecting lines and concurrently to form polysilicon landing plugs to the N− contacts, while forming metal landing plugs to the N+ and P+ contacts.