Patents by Inventor Errol Antonio C. Sanchez

Errol Antonio C. Sanchez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10770319
    Abstract: Embodiments described herein provide processing chambers that include an enclosure for a processing volume, a rotatable support within the enclosure, the support having a shaft that extends outside the enclosure, wherein the shaft has a signal feature located outside the processing volume, an energy module within the enclosure, wherein the shaft extends through the energy module, one or more directed energy sources coupled to the enclosure, and one or more signalers positioned proximate to the signal feature, each signaler coupled to at least one of the directed energy sources.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: September 8, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Shu-Kwan Danny Lau, Zhiyuan Ye, Zuoming Zhu, Nyi O. Myo, Errol Antonio C. Sanchez, Schubert S. Chu
  • Patent number: 10727093
    Abstract: Embodiments disclosed herein relate to a light pipe structure for thermal processing of semiconductor substrates. In one embodiment, a light pipe window structure for use in a thermal process chamber includes a transparent plate, and a plurality of light pipe structures formed in a transparent material that is coupled to the transparent plate, each of the plurality of light pipe structures comprising a reflective surface and having a longitudinal axis disposed in a substantially perpendicular relation to a plane of the transparent plate.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: July 28, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Paul Brillhart, Joseph M. Ranish, Aaron Muir Hunter, Edric Tong, James Francis Mack, Kin Pong Lo, Errol Antonio C. Sanchez, Zhiyuan Ye, Anzhong Chang
  • Publication number: 20200203149
    Abstract: Methods for forming films during semiconductor device fabrication by soaking a substrate in dopant are discussed herein. The dopant soak is performed in a process chamber using at least one dopant precursor for a predetermined period of time to form a dopant layer on the substrate. The process chamber is subsequently purged of the at least one dopant precursor. At least one film precursor is introduced into the process chamber after the process chamber is purged. A film is epitaxially formed on the substrate to have at least one of a target resistivity, dopant concentration, and/or thickness. Post-processing operations can include annealing or patterning the semiconductor film, or depositing additional layers thereon.
    Type: Application
    Filed: December 5, 2019
    Publication date: June 25, 2020
    Inventors: Yi-Chiau HUANG, Errol Antonio C SANCHEZ
  • Publication number: 20200091010
    Abstract: The systems and methods discussed herein are for a cluster tool that can be used for MOSFET device fabrication, including NMOS and PMOS devices. The cluster tool includes process chambers for pre-cleaning, metal-silicide or metal-germanide film formation, and surface protection operations such as capping and nitridation. The cluster tool can include one or more process chambers configured to form a source and a drain. The devices fabricated in the cluster tool are fabricated to have at least one protective layer formed over the metal-silicide or metal-germanide film to protect the film from contamination during handling and transfer to separate systems.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 19, 2020
    Inventors: Xuebin LI, Schubert S. CHU, Errol Antonio C. SANCHEZ, Patricia M. LIU, Gaurav THAREJA, Raymond HUNG
  • Publication number: 20200045776
    Abstract: A method and apparatus for processing a semiconductor substrate is described. A substrate processing apparatus is disclosed that includes a process chamber, a substrate support disposed inside the process chamber, a plurality of lamps arranged in a lamphead and positioned proximate to the substrate support, a gas source for providing a purge gas in a lateral flow path across the substrate support, and a controller that differentially adjusts power to individual lamps of the plurality of lamps based on a direction of the flow path.
    Type: Application
    Filed: August 1, 2019
    Publication date: February 6, 2020
    Inventors: Yi-Chiau HUANG, Errol Antonio C. SANCHEZ
  • Publication number: 20200035822
    Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Application
    Filed: October 3, 2019
    Publication date: January 30, 2020
    Inventors: Shiyu SUN, Naomi YOSHIDA, Theresa Kramer GUARINI, Sung Won JUN, Vanessa PENA, Errol Antonio C. SANCHEZ, Benjamin COLOMBEAU, Michael CHUDZIK, Bingxi WOOD, Nam Sung KIM
  • Publication number: 20200013624
    Abstract: Embodiments disclosed herein are directed to forming MOSFET devices. In particular, one or more pre-silicide treatments are performed on a substrate prior to the deposition of the metal-silicide layer to improve the density and performance of the metal-silicide layer in the MOSFETs. The metal-silicide formation formed with the pre-silicide treatment(s) can occur before or after the formation of metal gates during MOSFET fabrication.
    Type: Application
    Filed: May 1, 2019
    Publication date: January 9, 2020
    Inventors: Xuebin LI, Errol Antonio C. SANCHEZ, Patricia M. LIU
  • Patent number: 10519547
    Abstract: Embodiments of the present disclosure generally relate to a susceptor for thermal processing of semiconductor substrates. In one embodiment, the susceptor includes a first rim, an inner region coupled to and surrounded by the first rim, and one or more annular protrusions formed on the inner region. The one or more annular protrusions may be formed on the inner region at a location corresponding to the location where a valley is formed on the substrate, and the one or more annular protrusions help reduce or eliminate the formation of the valley.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: December 31, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Karthik Ramanathan, Kartik Shah, Nyi O. Myo, Schubert S. Chu, Jeffrey Tobin, Errol Antonio C. Sanchez, Palamurali Gajendra
  • Patent number: 10490666
    Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: November 26, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Shiyu Sun, Nam Sung Kim, Naomi Yoshida, Theresa Kramer Guarini, Sung Won Jun, Vanessa Pena, Errol Antonio C. Sanchez, Benjamin Colombeau, Michael Chudzik, Bingxi Wood
  • Patent number: 10458040
    Abstract: Embodiments provided herein generally relate to an apparatus for delivering gas to a semiconductor processing chamber. An upper quartz dome of an epitaxial semiconductor processing chamber has a plurality of holes formed therein and precursor gases are provided into a processing volume of the chamber through the holes of the upper dome. Gas delivery tubes extend from the holes in the dome to a flange plate where the tubes are coupled to gas delivery lines. The gas delivery apparatus enables gases to be delivered to the processing volume above a substrate through the quartz upper dome.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: October 29, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Paul Brillhart, Anzhong Chang, Edric Tong, Kin Pong Lo, James Francis Mack, Zhiyuan Ye, Kartik Shah, Errol Antonio C. Sanchez, David K. Carlson, Satheesh Kuppurao, Joseph M. Ranish
  • Publication number: 20190267263
    Abstract: Embodiments described herein provide processing chambers that include an enclosure for a processing volume, a rotatable support within the enclosure, the support having a shaft that extends outside the enclosure, wherein the shaft has a signal feature located outside the processing volume, an energy module within the enclosure, wherein the shaft extends through the energy module, one or more directed energy sources coupled to the enclosure, and one or more signalers positioned proximate to the signal feature, each signaler coupled to at least one of the directed energy sources.
    Type: Application
    Filed: February 12, 2019
    Publication date: August 29, 2019
    Inventors: Shu-Kwan Danny LAU, Zhiyuan YE, Zuoming ZHU, Nyi O. MYO, Errol Antonio C. SANCHEZ, Schubert S. CHU
  • Publication number: 20190127851
    Abstract: Embodiments of the present disclosure generally relate to apparatus and methods for semiconductor processing, more particularly, to a thermal process chamber. The thermal process chamber includes a substrate support, a first plurality of heating elements disposed over or below the substrate support, and a spot heating module disposed over the substrate support. The spot heating module is utilized to provide local heating of cold regions on a substrate disposed on the substrate support during processing. Localized heating of the substrate improves temperature profile, which in turn improves deposition uniformity.
    Type: Application
    Filed: October 25, 2018
    Publication date: May 2, 2019
    Inventors: Shu-Kwan LAU, Koji NAKANISHI, Toshiyuki NAKAGAWA, Zuoming ZHU, Zhiyuan YE, Joseph M. RANISH, Nyi O. MYO, Errol Antonio C. SANCHEZ, Schubert S. CHU
  • Patent number: 10276688
    Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: April 30, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xinyu Bao, Zhiyuan Ye, Flora Fong-Song Chang, Abhishek Dube, Xuebin Li, Errol Antonio C. Sanchez, Hua Chung, Schubert S. Chu
  • Publication number: 20190119814
    Abstract: Embodiments of a precursor feed system for a semiconductor process are described herein. The precursor feed system provides improved flow control of a vaporized precursor material to a process chamber by improving flow characteristics of vaporized precursor materials, carried by a carrier gas, which may be an inert gas. The precursor feed system also reduces an occurrence of a pressure drop in conduits that deliver the precursor to the process chamber. Reducing the occurrence of the pressure drop also reduces a decrease of energy from the gas, thus reducing a tendency of the gas to condense in the along the flow path.
    Type: Application
    Filed: October 16, 2018
    Publication date: April 25, 2019
    Inventors: Zhiyuan YE, Garry KWONG, Errol Antonio C. SANCHEZ, Nyi O. MYO
  • Patent number: 10205002
    Abstract: The present disclosure generally relate to methods of processing a substrate in an epitaxy chamber. The method includes exposing a substrate having one or more fins to a group IV-containing precursor and a surfactant containing antimony to form an epitaxial film over sidewalls of the one or more fin structures, wherein the surfactant containing antimony is introduced into the epitaxy chamber before epitaxial growth of the epitaxial film, and a molar ratio of the surfactant containing antimony to the group IV-containing precursor is about 0.0001 to about 10.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: February 12, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xinyu Bao, Chun Yan, Errol Antonio C. Sanchez, Hua Chung
  • Patent number: 10132003
    Abstract: Embodiments disclosed herein generally related to a processing chamber, and more specifically a heat modulator assembly for use in a processing chamber. The heat modulator assembly includes a heat modulator housing and a plurality of heat modulators. The heat modulator housing includes a housing member defining a housing plane, a sidewall, and an annular extension. The sidewall extends perpendicular to the housing plane. The annular extension extends outward from the sidewall. The plurality of heat modulators is positioned in the housing member.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: November 20, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Shu-Kwan Lau, Surajit Kumar, Joseph M. Ranish, Zhiyuan Ye, Kartik Shah, Mehmet Tugrul Samir, Errol Antonio C. Sanchez
  • Patent number: 10125415
    Abstract: Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: November 13, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Zhiyuan Ye, Errol Antonio C. Sanchez, Keun-Yong Ban, Xinyu Bao
  • Publication number: 20180286961
    Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.
    Type: Application
    Filed: February 14, 2018
    Publication date: October 4, 2018
    Inventors: Xinyu BAO, Zhiyuan YE, Flora Fong-Song CHANG, Abhishek DUBE, Xuebin LI, Errol Antonio C. SANCHEZ, Hua CHUNG, Schubert S. CHU
  • Patent number: 10043870
    Abstract: Embodiments of the present disclosure generally relate to a film stack including layers of group III-V semiconductor materials. The film stack includes a phosphorous containing layer deposited over a silicon substrate, a GaAs containing layer deposited on the phosphorous containing layer, and an aluminum containing layer deposited on the GaAs containing layer. The GaAs containing layer between the phosphorous containing layer and the aluminum containing layer improves the surface smoothness of the aluminum containing layer.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: August 7, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Zhiyuan Ye, Xinyu Bao, Errol Antonio C. Sanchez, David K. Carlson, Keun-Yong Ban
  • Patent number: 10043666
    Abstract: Embodiments described herein generally relate to a substrate processing system, such as an etch processing system. In one embodiment, a method of processing a substrate is disclosed herein. The method includes removing a native oxide from a surface of the substrate, baking the substrate in a pre-treatment thermal chamber such that double atomic steps are formed on the surface of the substrate, and forming an epitaxial layer on the substrate after the substrate is baked.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: August 7, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xinyu Bao, Errol Antonio C. Sanchez, Zhiyuan Ye, Keun-Yong Ban