Abstract: Apparatus for processing a substrate in a process chamber are provided here. In some embodiments, a gas injector for use in a process chamber includes a first set of outlet ports that provide an angled injection of a first process gas at an angle to a planar surface, and a second set of outlet ports proximate the first set of outlet ports that provide a pressurized laminar flow of a second process gas substantially along the planar surface, the planar surface extending normal to the second set of outlet ports.

Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.

Abstract: The present disclosure generally relate to methods of processing a substrate in an epitaxy chamber. The method includes applying a passivating agent containing antimony to portions of a silicon substrate exposed through trenches formed in a dielectric layer on the silicon substrate, while applying the passivating agent containing antimony, exposing the silicon substrate to a group IV-containing precursor to form an epitaxial layer having a V-shaped structure having an exposed (111) plane at a bottom of the trenches, and forming a semiconductor layer on the epitaxial layer.

Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.

Abstract: Embodiments provided herein generally relate to an apparatus for delivering gas to a semiconductor processing chamber. An upper quartz dome of an epitaxial semiconductor processing chamber has a plurality of holes formed therein and precursor gases are provided into a processing volume of the chamber through the holes of the upper dome. Gas delivery tubes extend from the holes in the dome to a flange plate where the tubes are coupled to gas delivery lines. The gas delivery apparatus enables gases to be delivered to the processing volume above a substrate through the quartz upper dome.

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Abstract: The present disclosure generally relate to methods of processing a substrate in an epitaxy chamber. The method includes exposing a substrate having one or more fins to a group IV-containing precursor and a surfactant containing antimony to form an epitaxial film over sidewalls of the one or more fin structures, wherein the surfactant containing antimony is introduced into the epitaxy chamber before epitaxial growth of the epitaxial film, and a molar ratio of the surfactant containing antimony to the group IV-containing precursor is about 0.0001 to about 10.

Abstract: The present disclosure generally relate to methods of processing a substrate in an epitaxy chamber. The method includes applying a passivating agent containing antimony to portions of a silicon substrate exposed through trenches formed in a dielectric layer on the silicon substrate, while applying the passivating agent containing antimony, exposing the silicon substrate to a group IV-containing precursor to form an epitaxial layer having a V-shaped structure having an exposed (111) plane at a bottom of the trenches, and forming a semiconductor layer on the epitaxial layer.

Abstract: Embodiments disclosed herein generally related to a processing chamber, and more specifically a heat modulator assembly for use in a processing chamber. The heat modulator assembly includes a heat modulator housing and a plurality of heat modulators. The heat modulator housing includes a housing member defining a housing plane, a sidewall, and an annular extension. The sidewall extends perpendicular to the housing plane. The annular extension extends outward from the sidewall. The plurality of heat modulators is positioned in the housing member.

Abstract: The present disclosure generally relate to methods for forming an epitaxial layer on a semiconductor device, including a method of forming a tensile-stressed silicon antimony layer. The method includes heating a substrate disposed within a processing chamber, wherein the substrate comprises silicon, and exposing a surface of the substrate to a gas mixture comprising a silicon-containing precursor and an antimony-containing precursor to form a silicon antimony alloy having an antimony concentration of 5×1020 to 5×1021 atoms per cubic centimeter or greater on the surface.

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Abstract: Embodiments of the disclosure relate to an apparatus for processing a semiconductor substrate. The apparatus includes a process chamber having a substrate support for supporting a substrate, a lower dome and an upper dome opposing the lower dome, a plurality of gas injects disposed within a sidewall of the process chamber. The apparatus includes a gas delivery system coupled to the process chamber via the plurality of gas injects, the gas delivery system includes a gas conduit providing one or more chemical species to the plurality of gas injects via a first fluid line, a dopant source providing one or more dopants to the plurality of gas injects via a second fluid line, and a fast switching valve disposed between the second fluid line and the process chamber, wherein the fast switching valve switches flowing of the one or more dopants between the process chamber and an exhaust.

Abstract: Embodiments provided herein generally relate to an apparatus for delivering gas to a semiconductor processing chamber. An upper quartz dome of an epitaxial semiconductor processing chamber has a plurality of holes formed therein and precursor gases are provided into a processing volume of the chamber through the holes of the upper dome. Gas delivery tubes extend from the holes in the dome to a flange plate where the tubes are coupled to gas delivery lines. The gas delivery apparatus enables gases to be delivered to the processing volume above a substrate through the quartz upper dome.

Abstract: Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.

Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.

Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.

Abstract: A method for forming a conformal group III/V layer on a silicon substrate and the resulting substrate with the group III/V layers formed thereon. The method includes removing the native oxide from the substrate, positioning a substrate within a processing chamber, heating the substrate to a first temperature, cooling the substrate to a second temperature, flowing a group III precursor into the processing chamber, maintaining the second temperature while flowing a group III precursor and a group V precursor into the processing chamber until a conformal layer is formed, heating the processing chamber to an annealing temperature, while stopping the flow of the group III precursor, and cooling the processing chamber to the second temperature. Deposition of the III/V layer may be made selective through the use of halide gas etching which preferentially etches dielectric regions.

Abstract: Embodiments described herein generally relate to a susceptor support for supporting a susceptor in a deposition process. The susceptor support includes a shaft, a plate with a first major surface coupled to the shaft, and a support element extending from a second major surface of the plate. The plate may be made of a material that is optically transparent to the radiation energy from a plurality of energy sources disposed below the plate. The plate may have a thickness that is small enough to minimize radiation transmission loss and large enough to be thermally and mechanically stable to support the susceptor during processing. The thickness of the plate may range from about 2 mm to about 20 mm.

Abstract: Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.

Abstract: Embodiments described herein generally relate to a substrate processing system, such as an etch processing system. In one embodiment, a method of processing a substrate is disclosed herein. The method includes removing a native oxide from a surface of the substrate, baking the substrate in a pre-treatment thermal chamber such that double atomic steps are formed on the surface of the substrate, and forming an epitaxial layer on the substrate after the substrate is baked.