Abstract: A semiconductor device comprising: a substrate having: a first terminal region; a second terminal region; a first extension region that extends from the first terminal region towards the second terminal region; a second extension region that extends from the second terminal region towards the first terminal region; a channel region between the first and second extension regions; a gate conductor that overlies the channel region of the substrate, the gate conductor configured to control conduction in the channel region; a first control conductor that overlies at least a portion of the first extension region, the first control conductor configured to control conduction in the first extension region; and a second control conductor that overlies at least a portion of the second extension region, the second control conductor configured to control conduction in the second extension region, wherein the first and second control conductors are electrically isolated within the semiconductor device from the gate conduct

Abstract: An integrated heat sink array is introduced in SOI power devices having multiple unit cells, which can be used to reduce the temperature rise in obtaining more uniform temperature peaks for all the unit cells across the device area, so that the hot spot which is prone to breakdown can be avoided, thus the safe operating area of the device can be improved. Also the array sacrifice less area of the device, therefore results in low Rdson.

Abstract: An integrated heat sink array is introduced in SOI power devices having multiple unit cells, which can be used to reduce the temperature rise in obtaining more uniform temperature peaks for all the unit cells across the device area, so that the hot spot which is prone to breakdown can be avoided, thus the safe operating area of the device can be improved. Also the array sacrifice less area of the device, therefore results in low Rdson.

Abstract: A semiconductor device comprising: a substrate having: a first terminal region; a second terminal region; a first extension region that extends from the first terminal region towards the second terminal region; a second extension region that extends from the second terminal region towards the first terminal region; a channel region between the first and second extension regions; a gate conductor that overlies the channel region of the substrate, the gate conductor configured to control conduction in the channel region; a first control conductor that overlies at least a portion of the first extension region, the first control conductor configured to control conduction in the first extension region; and a second control conductor that overlies at least a portion of the second extension region, the second control conductor configured to control conduction in the second extension region, wherein the first and second control conductors are electrically isolated within the semiconductor device from the gate conduct

Abstract: An integrated heat sink array is introduced in SOI power devices having multiple unit cells, which can be used to reduce the temperature rise in obtaining more uniform temperature peaks for all the unit cells across the device area, so that the hot spot which is prone to breakdown can be avoided, thus the safe operating area of the device can be improved. Also the array sacrifice less area of the device, therefore results in low Rdson.

Abstract: An integrated heat sink array is introduced in SOI power devices having multiple unit cells, which can be used to reduce the temperature rise in obtaining more uniform temperature peaks for all the unit cells across the device area, so that the hot spot which is prone to breakdown can be avoided, thus the safe operating area of the device can be improved. Also the array sacrifice less area of the device, therefore results in low Rdson.

Abstract: A method of manufacturing a structure (1100), the method comprising forming a cap element (401) on a substrate (101), removing material (103) of the substrate (101) below the cap element (401) to thereby form a gap (802) between the cap element (401) and the substrate (101), and rearranging material of the cap element (401) and/or of the substrate (101) to thereby merge the cap element (401) and the substrate (101) to bridge the gap (802).

Abstract: A semiconductor device (10) comprising a bipolar transistor and a field 5 effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22c and 22d) and a base region (33c) of the bipolar transistor. The bipolar transistor is provided with an insulating cavity (92b) provided in the collector region (22c and 22d). The insulating cavity (92b) may be provided by providing a layer (33a) in the collector region (22c), creating an access path, for example by selectively etching polysilicon towards monocrystalline, and removing a portion of the layer (33a) to provide the cavity using the access path. The layer (33a) provided in the collector region may be of SiGe:C. By blocking diffusion from the base region the insulating cavity (92b) provides a reduction in the base collector capacitance and can be described as defining the base contact.

Abstract: Disclosed is an integrated circuit (100) comprising a substrate (110) carrying a plurality of light-sensitive elements (112) and a blazed grating (120) comprising a plurality of diffractive elements (122) for diffracting respective spectral components (123-125) of incident light (150) to respective light-sensitive elements (112), the blazed grating (120) comprising a stack of layers, at least some of these layers comprising first portions, e.g. metal portions (202, 222, 242) arranged such that each diffractive element (122) comprises a stepped profile of stacked first portions with a first portion in a higher layer laterally extending beyond a first portion in a lower layer of said stepped profile.

Abstract: Methods for manufacturing a bipolar transistor semiconductor device are described, along with devices fabricated in accordance with the methods. The methods include the steps of forming a stack of layers over a semiconductor body comprising a window definition layer (18,38), a layer (20) of semiconductor material, a first insulating layer (22), and a second insulating layer (24) which is selectively etchable with respect to the first insulating layer. A trench (26) is then etched into the stack down to the window definition layer. The portion of the trench extending through the second insulating layer is widened to form a wider trench portion (28) therethrough. A window (36) is defined in the window definition layer which is aligned with the wider trench portion, and serves to define the base-collector or base-emitter junction in the finished device.

Abstract: The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (1) comprising a bipolar transistor with in that order a collector region (2), a base region (3), and an emitter region (4), wherein the semiconductor body comprises a projecting mesa (5) comprising at least a portion of the collector region (2) and the base region (3), which mesa is surrounded by an isolation region (6). According to the invention, the semiconductor device (10) also comprises a field effect transistor with a source region, a drain region, an interposed channel region, a superimposed gate dielectric (7), and a gate region (8), which gate region (8) forms a highest part of the field effect transistor, and the height of the mesa (5) is greater than the height of the gate region (8). This device can be manufactured inexpensively and easily by a method according to the invention, and the bipolar transistor can have excellent high-frequency characteristics.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) which is provided with at least one bipolar transistor having an emitter region (1), a base region (2) and a collector region (3), wherein in the semiconductor body (12) a first semiconductor region (13) is formed that forms one (3) of the collector and emitter regions (1,3) and on the surface of the semiconductor body (12) a stack of layers is formed comprising a first insulating layer (4), a polycrystalline semiconductor layer (5) and a second insulating layer (6) in which stack an opening (7) is formed, after which by non-selective epitaxial growth a further semiconductor layer (22) is deposited of which a monocrystalline horizontal part on the bottom of the opening (7) forms the base region (2) and of which a polycrystalline vertical part (2A) on a side face of the opening (7) is connected to the polycrystalline semiconductor layer (5), after which spacers (S) are formed paral

Abstract: Methods for manufacturing a bipolar transistor semiconductor device are described, along with devices fabricated in accordance with the methods. The methods include the steps of forming a stack of layers over a semiconductor body comprising a window definition layer (18,38), a layer (20) of semiconductor material, a first insulating layer (22), and a second insulating layer (24) which is selectively etchable with respect to the first insulating layer. A trench (26) is then etched into the stack down to the window definition layer. The portion of the trench extending through the second insulating layer is widened to form a wider trench portion (28) therethrough. A window (36) is defined in the window definition layer which is aligned with the wider trench portion, and serves to define the base-collector or base-emitter junction in the finished device.

Abstract: A semiconductor device (10) comprising a bipolar transistor and a field 5 effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22c and 22d) and a base region (33c) of the bipolar transistor. The bipolar transistor is provided with an insulating cavity (92b) provided in the collector region (22c and 22d). The insulating cavity (92b) may be provided by providing a layer (33a) in the collector region (22c), creating an access path, for example by selectively etching polysilicon towards monocrystalline, and removing a portion of the layer (33a) to provide the cavity using the access path. The layer (33a) provided in the collector region may be of SiGe:C. By blocking diffusion from the base region the insulating cavity (92b) provides a reduction in the base collector capacitance and can be described as defining the base contact.

Abstract: Disclosed is an integrated circuit (100) comprising a substrate (110) carrying a plurality of light-sensitive elements (112) and a blazed grating (120) comprising a plurality of diffractive elements (122) for diffracting respective spectral components (123-125) of incident light (150) to respective light-sensitive elements (112), the blazed grating (120) comprising a stack of layers, at least some of these layers comprising first portions, e.g. metal portions (202, 222, 242) arranged such that each diffractive element (122) comprises a stepped profile of stacked first portions with a first portion in a higher layer laterally extending beyond a first portion in a lower layer of said stepped profile.

Abstract: The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (12) of silicon which comprises an active region (A) with a transistor (T) and a passive region (P) surrounding the active region (A) and which is provided with a buried conducting region (1) of a metallic material that is connected to a conductive region (2) of a metallic material sunken from the surface of the semiconductor body (12), by which the buried conductive region (1) is made electrically connectable at the surface of the semiconductor body (12). According to the invention, the buried conducting region (1) is made at the location of the active region (A) of the semiconductor body (12). In this way, a very low buried resistance can be locally created in the active region (A) in the semiconductor body (12), using a metallic material that has completely different crystallographic properties from the surrounding silicon. This is made possible by using a method according to the invention.

Abstract: A method of manufacturing a bipolar transistor is compatible with FinFET processing. A collector region (18) is formed and patterned, base contact regions (26) formed on either side, and a gap formed between the base contact region. A base (28), spacers (30) and an emitter (32) are formed in the gap.

Abstract: The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region, a base region and a collector region (1, 2, 3) of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type, and the first conductivity type. One of the emitter or collector regions (1, 3) comprises a nanowire (30). The base region (2) has been formed from a layer (20) at the surface of the semiconductor body (12); the other one (3, 1) of the emitter or collector regions (1, 3) has been formed in the semiconductor body (12) below the base region (2). The emitter or collector region (1, 3) comprising the nanowire (30) has been provided on the surface of the semiconductor body (12) such that its longitudinal axis extends perpendicularly to the surface.

Abstract: A method of manufacturing a bipolar transistor is compatible with FinFET processing. A collector region (18) is formed and patterned, base contact regions (26) formed on either side, and a gap formed between the base contact region. A base (28), spacers (30) and an emitter (32) are formed in the gap.

Abstract: The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (12) comprising a vertical bipolar transistor with an emitter region, a base region and a collector region (1, 2, 3) of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type and the first conductivity type, wherein the collector region (3) comprises a first sub-region (3A) bordering the base region (2) and a second sub-region (3B) bordering the first sub-region (3A) which has a lower doping concentration than the second sub-region (3B), and the transistor is provided with a gate electrode (5) which laterally borders the first sub-region (3A) and by means of which the first sub-region (3A) may be depleted.