Abstract: An apparatus may include an electric power converter and pre-charge circuitry. The electric power converter may include a first circuit, a second circuit and an energy transfer device. The first circuit may be connected to a power supply. The second circuit may be connected to a load. The energy transfer device may have a first side connected to the first circuit and a second side connected to the second circuit. The pre-charge circuitry may be connected to a capacitor of the first circuit. The capacitor may be connected to the first side of the energy transfer device. The pre-charge circuitry may be configured to charge the capacitor during a pre-charge mode of the electric power converter. The electric power converter may be configured to exit the pre-charge mode and enter an energy transfer mode responsive to a charge level of the capacitor reaching a threshold pre-charge level.

Abstract: An apparatus may include an electric power converter and pre-charge circuitry. The electric power converter may include a first circuit, a second circuit and an energy transfer device. The first circuit may be connected to a power supply. The second circuit may be connected to a load. The energy transfer device may have a first side connected to the first circuit and a second side connected to the second circuit. The pre-charge circuitry may be connected to a capacitor of the first circuit. The capacitor may be connected to the first side of the energy transfer device. The pre-charge circuitry may be configured to charge the capacitor during a pre-charge mode of the electric power converter. The electric power converter may be configured to exit the pre-charge mode and enter an energy transfer mode responsive to a charge level of the capacitor reaching a threshold pre-charge level.

Abstract: A system and method for an overcurrent detector includes a device. The device includes a threshold generation circuit, and an overpower determination circuit. The threshold generation circuit is configured to produce a threshold value based on an output of a temperature sensor proximate to a power transistor, and a maximum power dissipation in the power transistor. The overpower determination circuit is configured to determine an overpower state of the power transistor based on the threshold value and a switch voltage. The switch voltage is detected between a source and a drain or a collector and an emitter of the power transistor.

Abstract: A system includes a control circuit having first and second detectors coupled to a first node of the control circuit, first and second filters coupled to the first and second detectors, and a logic circuit coupled to the first and second filters, a diode circuit having a first node coupled to the first node of the control circuit, and a switch having a first current node coupled to a second node of the diode circuit, a gate coupled to a second node of the control circuit, and a second current node coupled to a third node of the control circuit, wherein a first detector is used to provide a first event overcurrent signal and a second detector is used to provide a multiple event overcurrent signal or a warning signal.

Abstract: A system includes a control circuit having first and second detectors coupled to a first node of the control circuit, first and second filters coupled to the first and second detectors, and a logic circuit coupled to the first and second filters, a diode circuit having a first node coupled to the first node of the control circuit, and a switch having a first current node coupled to a second node of the diode circuit, a gate coupled to a second node of the control circuit, and a second current node coupled to a third node of the control circuit, wherein a first detector is used to provide a first event overcurrent signal and a second detector is used to provide a multiple event overcurrent signal or a warning signal.

Abstract: In accordance with an embodiment of the present invention, a circuit includes a configurable clamp driver circuit for clamping a voltage at a gate terminal of a transistor below a turn-on voltage threshold upon switch-off of the transistor. In a first clamp driver circuit mode, an output terminal of the clamp driver circuit is configured to be coupled to the gate terminal of the transistor to provide a first discharge path from the gate terminal of the transistor upon switch-off of the transistor. In a second clamp driver circuit mode, the output terminal of the clamp driver circuit is configured to be coupled to an input terminal of a clamp circuit, wherein the clamp circuit is coupled to the gate terminal of the transistor to provide a second discharge path from the gate terminal of the transistor upon switch-off of the transistor.

Abstract: A method for operating a gate driver circuit includes supplying power to the gate driver circuit from a power supply including a positive power supply voltage and a negative power supply voltage. The method also includes comparing the negative power supply voltage with a first voltage at an output terminal of a transistor, wherein the gate driver circuit is coupled to a gate terminal of the transistor. The method also includes operating the gate driver circuit when the negative power supply voltage is more negative than a trigger voltage, wherein the trigger voltage is a predetermined voltage above the first voltage. The method also includes deactivating at least a portion of the gate driver circuit when the negative power supply voltage is more positive than the trigger voltage.

Abstract: In accordance with an embodiment, a method of operating a control circuit includes generating a threshold value based on a drive signal of an external power transistor, and determining an overpower state of the external power transistor based on a voltage at a drain or a collector of the external power transistor and the threshold value.

Abstract: An embodiment bus device with a programmable address includes a bus communication circuit connected to a bus terminal, a first pin terminal, a memory having a first register with a first address stored therein and a second register, and a state logic circuit. The state logic circuit detects a chip select signal on the first pin terminal, receives a first message through the bus communication circuit while the chip select signal is asserted, determines that the first message indicates an address set command, and saves an address value in the first message as a second address in the second register in response to a target address in the first message matching the first address. The state logic circuit further processes a second message received through the bus communication circuit in response to a target address of the second message matching the second address.

Abstract: In accordance with an embodiment, a method of operating a control circuit includes generating a threshold value based on a drive signal of an external power transistor, and determining an overpower state of the external power transistor based on a voltage at a drain or a collector of the external power transistor and the threshold value.

Abstract: An embodiment bus device with a programmable address includes a bus communication circuit connected to a bus terminal, a first pin terminal, a memory having a first register with a first address stored therein and a second register, and a state logic circuit. The state logic circuit detects a chip select signal on the first pin terminal, receives a first message through the bus communication circuit while the chip select signal is asserted, determines that the first message indicates an address set command, and saves an address value in the first message as a second address in the second register in response to a target address in the first message matching the first address. The state logic circuit further processes a second message received through the bus communication circuit in response to a target address of the second message matching the second address.

Abstract: In accordance with an embodiment of the present invention, a circuit includes a configurable clamp driver circuit for clamping a voltage at a gate terminal of a transistor below a turn-on voltage threshold upon switch-off of the transistor. In a first clamp driver circuit mode, an output terminal of the clamp driver circuit is configured to be coupled to the gate terminal of the transistor to provide a first discharge path from the gate terminal of the transistor upon switch-off of the transistor. In a second clamp driver circuit mode, the output terminal of the clamp driver circuit is configured to be coupled to an input terminal of a clamp circuit, wherein the clamp circuit is coupled to the gate terminal of the transistor to provide a second discharge path from the gate terminal of the transistor upon switch-off of the transistor.

Abstract: A method for operating a gate driver circuit includes supplying power to the gate driver circuit from a power supply including a positive power supply voltage and a negative power supply voltage. The method also includes comparing the negative power supply voltage with a first voltage at an output terminal of a transistor, wherein the gate driver circuit is coupled to a gate terminal of the transistor. The method also includes operating the gate driver circuit when the negative power supply voltage is more negative than a trigger voltage, wherein the trigger voltage is a predetermined voltage above the first voltage. The method also includes deactivating at least a portion of the gate driver circuit when the negative power supply voltage is more positive than the trigger voltage.

Abstract: A system and method for an overcurrent detector includes a device. The device includes a threshold generation circuit, and an overpower determination circuit. The threshold generation circuit is configured to produce a threshold value based on an output of a temperature sensor proximate to a power transistor, and a maximum power dissipation in the power transistor. The overpower determination circuit is configured to determine an overpower state of the power transistor based on the threshold value and a switch voltage. The switch voltage is detected between a source and a drain or a collector and an emitter of the power transistor.

Abstract: An electronic module. One embodiment includes a carrier. A first transistor is attached to the carrier. A second transistor is attached to the carrier. A first connection element includes a first planar region. The first connection element electrically connects the first transistor to the carrier. A second connection element includes a second planar region. The second connection element electrically connects the second transistor to the carrier. In one embodiment, a distance between the first planar region and the second planar region is smaller than 100 ?m.

Abstract: An electronic module. One embodiment includes a carrier. A first transistor is attached to the carrier. A second transistor is attached to the carrier. A first connection element includes a first planar region. The first connection element electrically connects the first transistor to the carrier. A second connection element includes a second planar region. The second connection element electrically connects the second transistor to the carrier. In one embodiment, a distance between the first planar region and the second planar region is smaller than 100 ?m.

Abstract: A system and method for statistics recording of power devices is disclosed. A power circuit includes a power device to provide a specified electrical power to a load and a host controller coupled to the power device. The host controller is configured to provide issue instructions to and retrieve status information from the power device. A communications and control interface (CCI) is coupled between the power device and the host controller. The CCI is configured to operate as a communications interface between the power device and the host controller and to retrieve and store status information from the power device. The CCI may be capable of performing statistical analysis on the status information to help reduce the amount of information exchanged between the host controller and the power device, thereby reducing bandwidth requirements.

Abstract: An electronic module. One embodiment includes a carrier. A first transistor is attached to the carrier. A second transistor is attached to the carrier. A first connection element includes a first planar region. The first connection element electrically connects the first transistor to the carrier. A second connection element includes a second planar region. The second connection element electrically connects the second transistor to the carrier. In one embodiment, a distance between the first planar region and the second planar region is smaller than 100 ?m.

Abstract: A component includes a first semiconductor chip attached to a first carrier and second semiconductor chip attached to a second carrier. The first carrier has a first extension, which forms a first external contact element. The second carrier has a second extension, which forms a second external contact element. The first and the second carriers are arranged in such a way that the first and the second extension point in different directions.

Abstract: A multi-chip module includes at least one integrated circuit chip that is electrically connected to first external terminals of the multi-chip module and at least one power semiconductor chip that is electrically connected to second external terminals of the multi-chip module. All first external terminals of the multi-chip module are arranged in a contiguous region of an terminal area of the multi-chip module.