Patents by Inventor Etai Zaltsman
Etai Zaltsman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230267168Abstract: Embodiments of the present disclosure relate to a vector circuit in an accelerator circuit for performing vector and scalar operations. The vector circuit reads a subset of instructions from an instruction memory, each instruction including an identification of at least a portion of a first vector and an identification of at least a portion of a second vector. The vector circuit further receives a portion of input data from a data memory corresponding to the subset of instructions. The vector circuit performs a respective operation in accordance with each instruction on at least one first element of the first vector and at least one second element of the second vector to generate at least one output element of an output vector. Each instruction indicates positions in respective vectors for the at least one first element, the at least one second element and the at least one output element.Type: ApplicationFiled: February 18, 2022Publication date: August 24, 2023Inventors: Liran Fishel, Danny Gal, Nir Nissan, Etai Zaltsman
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Patent number: 11614937Abstract: Embodiments of the present disclosure relate to an accelerator circuit with a dynamic immediate values table (IVT). The accelerator circuit includes an instruction memory, a data memory, and a vector circuit with the IVT storing multiple immediate values at multiple entries. The vector circuit reads a subset of instructions from the instruction memory, each instruction including at least one corresponding pointer to at least one corresponding entry in the IVT. The vector circuit further receives a subset of input data from the data memory corresponding to the subset of instructions. The vector circuit performs a respective operation in accordance with each instruction from the subset of instructions using a corresponding data vector of the received subset of input data identified in each instruction and at least one corresponding immediate value from the IVT pointed by the at least one corresponding pointer to generate corresponding output data.Type: GrantFiled: December 30, 2021Date of Patent: March 28, 2023Assignee: Apple Inc.Inventors: Liran Fishel, Danny Gal, Nir Nissan, Etai Zaltsman
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Patent number: 10089266Abstract: Disclosed herein is a technique for maintaining a responsive user interface for a user while preserving battery life of a user device by dynamically determining the interrupt rate/interrupt time at the user device. Based on priority tier information associated with the I/O requests along with the directionality and size of the I/O requests, a determination can be made regarding how the interrupt rate/interrupt time can be adjusted to achieve acceptable user interface (UI) responsiveness and maximum power savings.Type: GrantFiled: July 10, 2015Date of Patent: October 2, 2018Assignee: Apple Inc.Inventors: Christopher J. Sarcone, Manoj K. Radhakrishnan, Etai Zaltsman
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Patent number: 10019196Abstract: A method in a storage device includes receiving from a host storage commands for execution in a non-volatile memory of the storage device. At least a subset of the storage commands are to be executed in accordance with an order-of-arrival in which the storage commands in the subset are received. The received storage commands are executed in the non-volatile memory in accordance with internal scheduling criteria of the storage device, which permit deviations from the order-of-arrival, but such that execution of the storage commands in the subset reflects the order-of-arrival to the host.Type: GrantFiled: July 30, 2015Date of Patent: July 10, 2018Assignee: Apple Inc.Inventors: Etai Zaltsman, Oren Golov, Ori Moshe Stern, Shai Ojalvo
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Patent number: 9996417Abstract: A controller includes an interface and a processor. The interface is configured to communicate with a memory including multiple memory cells organized in at least two sections each including multiple sets of word lines (WLs), wherein in a first failure mode multiple WLs fail in a single section, and in a second failure mode a WL fails in multiple sections. The processor is configured to assign multiple cell-groups of the memory cells to a parity-group, such that (i) no two cell-groups in the parity-group belong to a same WL, and (ii) no two cell-groups in the parity-group belong to adjacent WLs in a same section, and, upon detecting a failure to access a cell-group in the parity-group, due to either the first or second failure modes but not both failure modes occurring simultaneously, to recover the data stored in the cell-group using one or more remaining cell-groups in the parity-group.Type: GrantFiled: April 12, 2016Date of Patent: June 12, 2018Assignee: Apple Inc.Inventors: Assaf Shappir, Etai Zaltsman, Guy Ben-Yehuda
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Patent number: 9952779Abstract: A controller includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a link. The processor is configured to select at least first and second memory devices for writing, and to write at least first and second data units in sequence to the first memory device over the link, while avoiding writing to any of the other memory devices until transferal of the at least first and second data units over the link has been completed, to write at least one data unit to the second memory device after transferring the at least first and second data units to the first memory device, and, in response to verifying that the first memory device is ready to receive subsequent data, to write to the first memory device at least a third data unit.Type: GrantFiled: March 1, 2016Date of Patent: April 24, 2018Assignee: APPLE INC.Inventors: Yoni Labenski, Roman Gindin, Etai Zaltsman, Moti Altahan, Yoram Harel, Barak Baum
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Publication number: 20170293527Abstract: A controller includes an interface and a processor. The interface is configured to communicate with a memory including multiple memory cells organized in at least two sections each including multiple sets of word lines (WLs), wherein in a first failure mode multiple WLs fail in a single section, and in a second failure mode a WL fails in multiple sections. The processor is configured to assign multiple cell-groups of the memory cells to a parity-group, such that (i) no two cell-groups in the parity-group belong to a same WL, and (ii) no two cell-groups in the parity-group belong to adjacent WLs in a same section, and, upon detecting a failure to access a cell-group in the parity-group, due to either the first or second failure modes but not both failure modes occurring simultaneously, to recover the data stored in the cell-group using one or more remaining cell-groups in the parity-group.Type: ApplicationFiled: April 12, 2016Publication date: October 12, 2017Inventors: Assaf Shappir, Etai Zaltsman, Guy Ben-Yehuda
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Publication number: 20170255396Abstract: A controller includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a link. The processor is configured to select at least first and second memory devices for writing, and to write at least first and second data units in sequence to the first memory device over the link, while avoiding writing to any of the other memory devices until transferal of the at least first and second data units over the link has been completed, to write at least one data unit to the second memory device after transferring the at least first and second data units to the first memory device, and, in response to verifying that the first memory device is ready to receive subsequent data, to write to the first memory device at least a third data unit.Type: ApplicationFiled: March 1, 2016Publication date: September 7, 2017Inventors: Yoni Labenski, Roman Gindin, Etai Zaltsman, Moti Altahan, Yoram Harel, Barak Baum
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Patent number: 9696918Abstract: A method for data storage includes, for a memory including groups of memory cells, defining a normal mode and a protected mode, wherein in the protected mode a respective analog value of each memory cell remains at all times unambiguously indicative of a respective data value stored in that memory cell. Data is initially stored in the memory using the normal mode. In response to an event, the protected mode is reverted to for at least one of the groups of the memory cells.Type: GrantFiled: October 27, 2014Date of Patent: July 4, 2017Assignee: APPLE INC.Inventors: Etai Zaltsman, Avraham Poza Meir
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Publication number: 20170010992Abstract: Disclosed herein is a technique for maintaining a responsive user interface for a user while preserving battery life of a user device by dynamically determining the interrupt rate/interrupt time at the user device. Based on priority tier information associated with the I/O requests along with the directionality and size of the I/O requests, a determination can be made regarding how the interrupt rate/interrupt time can be adjusted to achieve acceptable user interface (UI) responsiveness and maximum power savings.Type: ApplicationFiled: July 10, 2015Publication date: January 12, 2017Inventors: Christopher J. SARCONE, Manoj K. RADHAKRISHNAN, Etai ZALTSMAN
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Patent number: 9535628Abstract: An apparatus includes a non-volatile memory and a processor. The processor is configured to receive, from a host, commands for storage of data in the non-volatile memory, to further receive from the host, for storage in the non-volatile memory, File System (FS) information that specifies organization of the data in a FS of the host, to receive from the host a directive that grants the processor permission and capability to access and modify the FS information, and to access the FS information, using the directive, so as to manage the storage of the data in the non-volatile memory.Type: GrantFiled: October 10, 2013Date of Patent: January 3, 2017Assignee: Apple Inc.Inventors: Etai Zaltsman, Sasha Paley, Avraham Poza Meir
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Patent number: 9465552Abstract: A method includes, in a memory controller that controls a memory, evaluating an available memory space remaining in the memory to write data. A redundant storage configuration is selected in the memory controller depending on the available memory space. Redundancy information is calculated over the data using the selected redundant storage configuration. The data and the redundancy information are written to the available memory space in the memory.Type: GrantFiled: August 3, 2015Date of Patent: October 11, 2016Assignee: Apple Inc.Inventors: Avraham Poza Meir, Oren Golov, Sasha Paley, Ori Moshe Stern, Etai Zaltsman
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Patent number: 9455040Abstract: A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.Type: GrantFiled: December 8, 2015Date of Patent: September 27, 2016Assignee: Apple Inc.Inventors: Yael Shur, Yoav Kasorla, Moshe Neerman, Naftali Sommer, Avraham Poza Meir, Etai Zaltsman, Eyal Gurgi, Meir Dalal
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Publication number: 20160147444Abstract: A method for data storage includes, in a memory that includes multiple memory blocks, assessing a performance characteristic of the multiple memory blocks. At least some of the memory blocks are grouped into groups using a grouping criterion that groups together the memory blocks based on similarity in the assessed performance characteristic. Data is stored in the memory by applying parallel memory access operations in the groups of the memory blocks.Type: ApplicationFiled: November 23, 2014Publication date: May 26, 2016Inventors: Moshe Neerman, Etai Zaltsman, Avraham (Poza) Meir
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Publication number: 20160093386Abstract: A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.Type: ApplicationFiled: December 8, 2015Publication date: March 31, 2016Inventors: Yael Shur, Yoav Kasorla, Moshe Neerman, Naftali Sommer, Avraham Poza Meir, Etai Zaltsman, Eyal Gurgi, Meir Dalal
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Publication number: 20160011806Abstract: A method for data storage includes, for a memory including groups of memory cells, defining a normal mode and a protected mode, wherein in the protected mode a respective analog value of each memory cell remains at all times unambiguously indicative of a respective data value stored in that memory cell. Data is initially stored in the memory using the normal mode. In response to an event, the protected mode is reverted to for at least one of the groups of the memory cells.Type: ApplicationFiled: October 27, 2014Publication date: January 14, 2016Inventors: Etai Zaltsman, Avraham Poza Meir
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Patent number: 9236132Abstract: A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.Type: GrantFiled: April 10, 2014Date of Patent: January 12, 2016Assignee: Apple Inc.Inventors: Yael Shur, Yoav Kasorla, Moshe Neerman, Naftali Sommer, Avraham Poza Meir, Etai Zaltsman, Eyal Gurgi, Meir Dalal
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Publication number: 20150339073Abstract: A method includes, in a memory controller that controls a memory, evaluating an available memory space remaining in the memory to write data. A redundant storage configuration is selected in the memory controller depending on the available memory space. Redundancy information is calculated over the data using the selected redundant storage configuration. The data and the redundancy information are written to the available memory space in the memory.Type: ApplicationFiled: August 3, 2015Publication date: November 26, 2015Inventors: Avraham Poza Meir, Oren Golov, Sasha Paley, Ori Moshe Stern, Etai Zaltsman
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Publication number: 20150331638Abstract: A method in a storage device includes receiving from a host storage commands for execution in a non-volatile memory of the storage device. At least a subset of the storage commands are to be executed in accordance with an order-of-arrival in which the storage commands in the subset are received. The received storage commands are executed in the non-volatile memory in accordance with internal scheduling criteria of the storage device, which permit deviations from the order-of-arrival, but such that execution of the storage commands in the subset reflects the order-of-arrival to the host.Type: ApplicationFiled: July 30, 2015Publication date: November 19, 2015Inventors: Etai Zaltsman, Oren Golov, Ori Moshe Stern, Shai Ojalvo
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Patent number: 9122401Abstract: A method in a storage device includes receiving from a host storage commands for execution in a non-volatile memory of the storage device. At least a subset of the storage commands are to be executed in accordance with an order-of-arrival in which the storage commands in the subset are received. The received storage commands are executed in the non-volatile memory in accordance with internal scheduling criteria of the storage device, which permit deviations from the order-of-arrival, but such that execution of the storage commands in the subset reflects the order-of-arrival to the host.Type: GrantFiled: August 23, 2012Date of Patent: September 1, 2015Assignee: Apple Inc.Inventors: Etai Zaltsman, Oren Golov, Ori Moshe Stern, Shai Ojalvo