Patents by Inventor Etsuko Fujimoto

Etsuko Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160377918
    Abstract: It is an object to provide a display having high visibility and a transflective type liquid crystal display device having a reflection electrode having a concavo-convex structure formed without especially increasing the process. During manufacturing a transflective liquid crystal display device, a reflection electrode of a plurality of irregularly arranged island-like patterns and a transparent electrode of a transparent conductive film are layered in forming an electrode having transparent and reflection electrodes thereby having a concavo-convex form to enhance the scattering ability of light and hence the visibility of display. Furthermore, because the plurality of irregularly arranged island-like patterns can be formed simultaneous with an interconnection, a concavo-convex structure can be formed during the manufacturing process without especially increasing the patterning process only for forming a concavo-convex structure. It is accordingly possible to greatly reduce cost and improve productivity.
    Type: Application
    Filed: September 13, 2016
    Publication date: December 29, 2016
    Inventors: Shunpei YAMAZAKI, Shingo Eguchi, Yutaka Shionoiri, Etsuko Fujimoto
  • Patent number: 9448432
    Abstract: It is an object to provide a display having high visibility and a transflective type liquid crystal display device having a reflection electrode having a concavo-convex structure formed without especially increasing the process. During manufacturing a transflective liquid crystal display device, a reflection electrode of a plurality of irregularly arranged island-like patterns and a transparent electrode of a transparent conductive film are layered in forming an electrode having transparent and reflection electrodes thereby having a concavo-convex form to enhance the scattering ability of light and hence the visibility of display. Furthermore, because the plurality of irregularly arranged island-like patterns can be formed simultaneous with an interconnection, a concavo-convex structure can be formed during the manufacturing process without especially increasing the patterning process only for forming a concavo-convex structure. It is accordingly possible to greatly reduce cost and improve productivity.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: September 20, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shingo Eguchi, Yutaka Shionoiri, Etsuko Fujimoto
  • Patent number: 8659025
    Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: February 25, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Etsuko Fujimoto, Satoshi Murakami, Shunpei Yamazaki, Shingo Eguchi
  • Patent number: 8502232
    Abstract: A highly reliable capacitor, a semiconductor device having high operating performance and reliability, and a manufacturing method thereof are provided. A capacitor formed of a first conductive film 102, a dielectric 103 made of an insulating material, and a second conductive film 104 is characterized in that a pin hole 106 formed by chance in the dielectric 103 is filled up with an insulating material (filler) 107 made of a resin material. This can prevent short circuit between the first conductive film 102 and the second conductive film 104. The capacitor is used as a storage capacitor provided in a pixel of a semiconductor device.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: August 6, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Murakami, Yoshiharu Hirakata, Etsuko Fujimoto, Yu Yamazaki, Shunpei Yamazaki
  • Publication number: 20130001561
    Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 3, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Etsuko Fujimoto, Satoshi Murakami, Shunpei Yamazaki, Shingo Eguchi
  • Patent number: 8278160
    Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: October 2, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Etsuko Fujimoto, Satoshi Murakami, Shunpei Yamazaki, Shingo Eguchi
  • Publication number: 20120142178
    Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.
    Type: Application
    Filed: February 15, 2012
    Publication date: June 7, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Etsuko Fujimoto, Satoshi Murakami, Shunpei Yamazaki, Shingo Eguchi
  • Patent number: 8134157
    Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: March 13, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Etsuko Fujimoto, Satoshi Murakami, Shunpei Yamazaki, Shingo Eguchi
  • Publication number: 20110254009
    Abstract: The object is to pattern extremely fine integrated circuits by forming fine contact holes. The dry etching method is employed to form contact holes to pattern a wiring (114), using a mask made of metallic film (112) and an organic material as an inter-layer insulating film (111) for covering switching elements and each of the wirings.
    Type: Application
    Filed: June 27, 2011
    Publication date: October 20, 2011
    Inventors: Hisashi Ohtani, Misako Nakazawa, Satoshi Murakami, Etsuko Fujimoto
  • Patent number: 7993992
    Abstract: There is disclosed a method of fabricating TFTs having reduced interconnect resistance by having improved contacts to source/drain regions. A silicide layer is formed in intimate contact with the source/drain regions. The remaining metallization layer is selectively etched to form a contact pad or conductive interconnects.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: August 9, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Etsuko Fujimoto
  • Publication number: 20110001140
    Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.
    Type: Application
    Filed: September 9, 2010
    Publication date: January 6, 2011
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Etsuko Fujimoto, Satoshi Murakami, Shunpei Yamazaki, Shingo Eguchi
  • Patent number: 7800115
    Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: September 21, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Etsuko Fujimoto, Satoshi Murakami, Shunpei Yamazaki, Shingo Eguchi
  • Patent number: 7709844
    Abstract: A semiconductor device and a process for production thereof, said semiconductor device having a new electrode structure which has a low resistivity and withstands heat treatment at 400° C. and above. Heat treatment at a high temperature (400-700° C.) is possible because the wiring is made of Ta film or Ta-based film having high heat resistance. This heat treatment permits the gettering of metal element in crystalline silicon film. Since this heat treatment is lower than the temperature which the gate wiring (0.1-5 ?m wide) withstands and the gate wiring is protected with a protective film, the gate wiring retains its low resistance.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: May 4, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd
    Inventors: Shunpei Yamazaki, Etsuko Fujimoto, Atsuo Isobe, Toru Takayama, Kunihiko Fukuchi
  • Publication number: 20100055852
    Abstract: There is disclosed a method of fabricating TFTs having reduced interconnect resistance by having improved contacts to source/drain regions. A silicide layer is formed in intimate contact with the source/drain regions. The remaining metallization layer is selectively etched to form a contact pad or conductive interconnects.
    Type: Application
    Filed: November 10, 2009
    Publication date: March 4, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hisashi Ohtani, Etsuko Fujimoto
  • Patent number: 7622740
    Abstract: There is disclosed a method of fabricating TFTs having reduced interconnect resistance by having improved contacts to source/drain regions. A silicide layer is formed in intimate contact with the source/drain regions. The remaining metallization layer is selectively etched to form a contact pad or conductive interconnects.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: November 24, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Etsuko Fujimoto
  • Publication number: 20090179205
    Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.
    Type: Application
    Filed: March 18, 2009
    Publication date: July 16, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Etsuko Fujimoto, Satoshi Murakami, Shunpei Yamazaki, Shingo Eguchi
  • Patent number: 7537972
    Abstract: The present invention provides the structure and manufacturing method of a semiconductor device that consumes small power even when a screen is made to be larger. A signal wiring line or a part of a gate wiring line is formed from a low resistant material (typically aluminum) and p-channel TFTs are used for a pixel TFT of a pixel portion. The p-channel TFT in the pixel portion has a multi-gate structure in which a plurality of channel formation regions are provided in order to reduce fluctuation in OFF current.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: May 26, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Etsuko Fujimoto, Satoshi Murakami, Hideomi Suzawa, Koji Ono
  • Patent number: 7511303
    Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: March 31, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Etsuko Fujimoto, Satoshi Murakami, Shunpei Yamazaki, Shingo Eguchi
  • Publication number: 20080174710
    Abstract: A highly reliable capacitor, a semiconductor device having high operating performance and reliability, and a manufacturing method thereof are provided. A capacitor formed of a first conductive film 102, a dielectric 103 made of an insulating material, and a second conductive film 104 is characterized in that a pin hole 106 formed by chance in the dielectric 103 is filled up with an insulating material (filler) 107 made of a resin material. This can prevent short circuit between the first conductive film 102 and the second conductive film 104. The capacitor is used as a storage capacitor provided in a pixel of a semiconductor device.
    Type: Application
    Filed: March 14, 2008
    Publication date: July 24, 2008
    Inventors: Satoshi Murakami, Yoshiharu Hirakata, Etsuko Fujimoto, Yu Yamazaki, Shunpei Yamazaki
  • Patent number: 7391055
    Abstract: A highly reliable capacitor, a semiconductor device having high operating performance and reliability, and a manufacturing method thereof are provided. A capacitor formed of a first conductive film 102, a dielectric 103 made of an insulating material, and a second conductive film 104 is characterized in that a pin hole 106 formed by chance in the dielectric 103 is filled up with an insulating material (filler) 107 made of a resin material. This can prevent short circuit between the first conductive film 102 and the second conductive film 104. The capacitor is used as a storage capacitor provided in a pixel of a semiconductor device.
    Type: Grant
    Filed: May 12, 2000
    Date of Patent: June 24, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Murakami, Yoshiharu Hirakata, Etsuko Fujimoto, Yu Yamazaki, Shunpei Yamazaki