Patents by Inventor Etsuko Fujimoto
Etsuko Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160377918Abstract: It is an object to provide a display having high visibility and a transflective type liquid crystal display device having a reflection electrode having a concavo-convex structure formed without especially increasing the process. During manufacturing a transflective liquid crystal display device, a reflection electrode of a plurality of irregularly arranged island-like patterns and a transparent electrode of a transparent conductive film are layered in forming an electrode having transparent and reflection electrodes thereby having a concavo-convex form to enhance the scattering ability of light and hence the visibility of display. Furthermore, because the plurality of irregularly arranged island-like patterns can be formed simultaneous with an interconnection, a concavo-convex structure can be formed during the manufacturing process without especially increasing the patterning process only for forming a concavo-convex structure. It is accordingly possible to greatly reduce cost and improve productivity.Type: ApplicationFiled: September 13, 2016Publication date: December 29, 2016Inventors: Shunpei YAMAZAKI, Shingo Eguchi, Yutaka Shionoiri, Etsuko Fujimoto
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Patent number: 9448432Abstract: It is an object to provide a display having high visibility and a transflective type liquid crystal display device having a reflection electrode having a concavo-convex structure formed without especially increasing the process. During manufacturing a transflective liquid crystal display device, a reflection electrode of a plurality of irregularly arranged island-like patterns and a transparent electrode of a transparent conductive film are layered in forming an electrode having transparent and reflection electrodes thereby having a concavo-convex form to enhance the scattering ability of light and hence the visibility of display. Furthermore, because the plurality of irregularly arranged island-like patterns can be formed simultaneous with an interconnection, a concavo-convex structure can be formed during the manufacturing process without especially increasing the patterning process only for forming a concavo-convex structure. It is accordingly possible to greatly reduce cost and improve productivity.Type: GrantFiled: May 15, 2006Date of Patent: September 20, 2016Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Shingo Eguchi, Yutaka Shionoiri, Etsuko Fujimoto
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Patent number: 8659025Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.Type: GrantFiled: September 13, 2012Date of Patent: February 25, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Etsuko Fujimoto, Satoshi Murakami, Shunpei Yamazaki, Shingo Eguchi
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Patent number: 8502232Abstract: A highly reliable capacitor, a semiconductor device having high operating performance and reliability, and a manufacturing method thereof are provided. A capacitor formed of a first conductive film 102, a dielectric 103 made of an insulating material, and a second conductive film 104 is characterized in that a pin hole 106 formed by chance in the dielectric 103 is filled up with an insulating material (filler) 107 made of a resin material. This can prevent short circuit between the first conductive film 102 and the second conductive film 104. The capacitor is used as a storage capacitor provided in a pixel of a semiconductor device.Type: GrantFiled: March 14, 2008Date of Patent: August 6, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoshi Murakami, Yoshiharu Hirakata, Etsuko Fujimoto, Yu Yamazaki, Shunpei Yamazaki
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Publication number: 20130001561Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.Type: ApplicationFiled: September 13, 2012Publication date: January 3, 2013Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Etsuko Fujimoto, Satoshi Murakami, Shunpei Yamazaki, Shingo Eguchi
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Patent number: 8278160Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.Type: GrantFiled: February 15, 2012Date of Patent: October 2, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Etsuko Fujimoto, Satoshi Murakami, Shunpei Yamazaki, Shingo Eguchi
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Publication number: 20120142178Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.Type: ApplicationFiled: February 15, 2012Publication date: June 7, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Etsuko Fujimoto, Satoshi Murakami, Shunpei Yamazaki, Shingo Eguchi
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Patent number: 8134157Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.Type: GrantFiled: September 9, 2010Date of Patent: March 13, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Etsuko Fujimoto, Satoshi Murakami, Shunpei Yamazaki, Shingo Eguchi
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Publication number: 20110254009Abstract: The object is to pattern extremely fine integrated circuits by forming fine contact holes. The dry etching method is employed to form contact holes to pattern a wiring (114), using a mask made of metallic film (112) and an organic material as an inter-layer insulating film (111) for covering switching elements and each of the wirings.Type: ApplicationFiled: June 27, 2011Publication date: October 20, 2011Inventors: Hisashi Ohtani, Misako Nakazawa, Satoshi Murakami, Etsuko Fujimoto
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Patent number: 7993992Abstract: There is disclosed a method of fabricating TFTs having reduced interconnect resistance by having improved contacts to source/drain regions. A silicide layer is formed in intimate contact with the source/drain regions. The remaining metallization layer is selectively etched to form a contact pad or conductive interconnects.Type: GrantFiled: November 10, 2009Date of Patent: August 9, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hisashi Ohtani, Etsuko Fujimoto
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Publication number: 20110001140Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.Type: ApplicationFiled: September 9, 2010Publication date: January 6, 2011Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Etsuko Fujimoto, Satoshi Murakami, Shunpei Yamazaki, Shingo Eguchi
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Patent number: 7800115Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.Type: GrantFiled: March 18, 2009Date of Patent: September 21, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Etsuko Fujimoto, Satoshi Murakami, Shunpei Yamazaki, Shingo Eguchi
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Patent number: 7709844Abstract: A semiconductor device and a process for production thereof, said semiconductor device having a new electrode structure which has a low resistivity and withstands heat treatment at 400° C. and above. Heat treatment at a high temperature (400-700° C.) is possible because the wiring is made of Ta film or Ta-based film having high heat resistance. This heat treatment permits the gettering of metal element in crystalline silicon film. Since this heat treatment is lower than the temperature which the gate wiring (0.1-5 ?m wide) withstands and the gate wiring is protected with a protective film, the gate wiring retains its low resistance.Type: GrantFiled: July 5, 2006Date of Patent: May 4, 2010Assignee: Semiconductor Energy Laboratory Co., LtdInventors: Shunpei Yamazaki, Etsuko Fujimoto, Atsuo Isobe, Toru Takayama, Kunihiko Fukuchi
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Publication number: 20100055852Abstract: There is disclosed a method of fabricating TFTs having reduced interconnect resistance by having improved contacts to source/drain regions. A silicide layer is formed in intimate contact with the source/drain regions. The remaining metallization layer is selectively etched to form a contact pad or conductive interconnects.Type: ApplicationFiled: November 10, 2009Publication date: March 4, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hisashi Ohtani, Etsuko Fujimoto
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Patent number: 7622740Abstract: There is disclosed a method of fabricating TFTs having reduced interconnect resistance by having improved contacts to source/drain regions. A silicide layer is formed in intimate contact with the source/drain regions. The remaining metallization layer is selectively etched to form a contact pad or conductive interconnects.Type: GrantFiled: May 18, 2007Date of Patent: November 24, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hisashi Ohtani, Etsuko Fujimoto
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Publication number: 20090179205Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.Type: ApplicationFiled: March 18, 2009Publication date: July 16, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Etsuko Fujimoto, Satoshi Murakami, Shunpei Yamazaki, Shingo Eguchi
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Patent number: 7537972Abstract: The present invention provides the structure and manufacturing method of a semiconductor device that consumes small power even when a screen is made to be larger. A signal wiring line or a part of a gate wiring line is formed from a low resistant material (typically aluminum) and p-channel TFTs are used for a pixel TFT of a pixel portion. The p-channel TFT in the pixel portion has a multi-gate structure in which a plurality of channel formation regions are provided in order to reduce fluctuation in OFF current.Type: GrantFiled: May 20, 2005Date of Patent: May 26, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Etsuko Fujimoto, Satoshi Murakami, Hideomi Suzawa, Koji Ono
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Patent number: 7511303Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.Type: GrantFiled: February 2, 2007Date of Patent: March 31, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Etsuko Fujimoto, Satoshi Murakami, Shunpei Yamazaki, Shingo Eguchi
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Publication number: 20080174710Abstract: A highly reliable capacitor, a semiconductor device having high operating performance and reliability, and a manufacturing method thereof are provided. A capacitor formed of a first conductive film 102, a dielectric 103 made of an insulating material, and a second conductive film 104 is characterized in that a pin hole 106 formed by chance in the dielectric 103 is filled up with an insulating material (filler) 107 made of a resin material. This can prevent short circuit between the first conductive film 102 and the second conductive film 104. The capacitor is used as a storage capacitor provided in a pixel of a semiconductor device.Type: ApplicationFiled: March 14, 2008Publication date: July 24, 2008Inventors: Satoshi Murakami, Yoshiharu Hirakata, Etsuko Fujimoto, Yu Yamazaki, Shunpei Yamazaki
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Patent number: 7391055Abstract: A highly reliable capacitor, a semiconductor device having high operating performance and reliability, and a manufacturing method thereof are provided. A capacitor formed of a first conductive film 102, a dielectric 103 made of an insulating material, and a second conductive film 104 is characterized in that a pin hole 106 formed by chance in the dielectric 103 is filled up with an insulating material (filler) 107 made of a resin material. This can prevent short circuit between the first conductive film 102 and the second conductive film 104. The capacitor is used as a storage capacitor provided in a pixel of a semiconductor device.Type: GrantFiled: May 12, 2000Date of Patent: June 24, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoshi Murakami, Yoshiharu Hirakata, Etsuko Fujimoto, Yu Yamazaki, Shunpei Yamazaki