Patents by Inventor Etsuko Fujimoto

Etsuko Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6586766
    Abstract: The invention is to provide a high-productivity method for fabricating a TFT device having different LDD structures on one and the same substrate, and the TFT device. Specifically, the invention provides a novel TFT structure, and a high-productivity method for fabricating it. A Ta film or a Ta-based film having good heat resistance is used for forming interconnections, and the interconnections are covered with a protective film. The interconnections can be subjected to heat treatment at high temperatures (400 to 700° C.), and, in addition, the protective film serves as an etching stopper. In the peripheral driving circuit portion in the device, TFTs having an LDD structure are disposed in a self-aligned process in which is used side walls 126 and 127; while in the pixel matrix portion therein, TFTs having an LDD structure are disposed in a non-self-aligned process in which is used an insulator 125.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: July 1, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Etsuko Fujimoto, Atsuo Isobe, Toru Takayama, Kunihiko Fukuchi
  • Patent number: 6576924
    Abstract: A semiconductor device in which TFTs of suitable structures are arranged depending upon the performances of the circuits, and storage capacitors are formed occupying small areas, the semiconductor device featuring high performance and bright image. The thickness of the gate-insulating film is differed depending upon a circuit that gives importance to the operation speed and a circuit that gives importance to the gate-insulating breakdown voltage, and the position for forming the LDD region is differed depending upon the TFT that gives importance to the countermeasure against the hot carriers and the TFT that gives importance to the countermeasure against the off current. This makes it possible to realize a semiconductor device of high performance. Further, the storage capacity is formed by a light-shielding film and an oxide thereof to minimize its area, and a semiconductor device capable of displaying a bright picture is realized.
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: June 10, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yukio Tanaka, Jun Koyama, Mitsuaki Osame, Satoshi Murakami, Hideto Ohnuma, Etsuko Fujimoto, Hidehito Kitakado
  • Publication number: 20030094614
    Abstract: The present invention provides the structure and manufacturing method of a semiconductor device that consumes small power even when a screen is made to be larger. A signal wiring line or a part of a gate wiring line is formed from a low resistant material (typically aluminum) and p-channel TFTs are used for a pixel TFT of a pixel portion. The p-channel TFT in the pixel portion has a multi-gate structure in which a plurality of channel formation regions are provided in order to reduce fluctuation in OFF current.
    Type: Application
    Filed: November 14, 2001
    Publication date: May 22, 2003
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Etsuko Fujimoto, Satoshi Murakami, Hideomi Suzawa, Koji Ono
  • Patent number: 6552362
    Abstract: To provide a semiconductor device having a large aperture ratio, in which an auxiliary capacitance of a large capacity is provided in each pixel. Capacitance wiring 102 comprising a tantalum film is formed on a substrate 101 having an insulating surface, and a tantalum oxide film 103 is formed by heat oxidation thereof. An active layer 104 comprising a semiconductor thin film is formed, and an auxiliary capacitance comprising the structure obtained by sandwiching the tantalum oxide film 103 with a part of the active layer 104 and the capacitance wiring 102 is formed. The active layer 104 functions as an active layer of a top-gate TFT.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: April 22, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Etsuko Fujimoto
  • Publication number: 20020149016
    Abstract: The invention is to provide a high-productivity method for fabricating a TFT device having different LDD structures on one and the same substrate, and the TFT device. Specifically, the invention provides a novel TFT structure, and a high-productivity method for fabricating it. A Ta film or a Ta-based film having good heat resistance is used for forming interconnections, and the interconnections are covered with a protective film. The interconnections can be subjected to heat treatment at high temperatures (400 to 700° C.), and, in addition, the protective film serves as an etching stopper. In the peripheral driving circuit portion in the device, TFTs having an LDD structure are disposed in a self-aligned process in which is used side walls 126 and 127; while in the pixel matrix portion therein, TFTs having an LDD structure are disposed in a non-self-aligned process in which is used an insulator 125.
    Type: Application
    Filed: April 18, 2002
    Publication date: October 17, 2002
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Etsuko Fujimoto, Atsuo Isobe, Toru Takayama, Kunihiko Fukuchi
  • Publication number: 20020102783
    Abstract: According to the present invention, a pixel TFT (an n-channel TFT) having a considerably low OFF current value and a high ratio of an ON current value to an OFF current value can be realized. In a pixel portion, an electrode having a taper portion with a width of 1&mgr;m or more is formed. An impurity region is formed by adding an impurity through the taper portion, so that the impurity region has a concentration gradient. Then, only the taper portion is removed to form the pixel TFT in the pixel portion. In the impurity region of the pixel TFT in the pixel portion, the concentration gradient is provided in a concentration distribution of the impurity imparting one conductivity, whereby a concentration is made small on the side of a channel forming region and a concentration is made large on the side of a semiconductor layer end portion.
    Type: Application
    Filed: October 24, 2001
    Publication date: August 1, 2002
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Etsuko Fujimoto, Satoshi Murakami, Akira Tsunoda
  • Publication number: 20020096681
    Abstract: A TFT using an aluminum material for a gate electrode is manufactured at a high yield factor. The gate electrode provided over an active layer and a gate insulating film is constituted by a lamination film of a tantalum layer and an aluminum layer. In this structure, the tantalum layer functions as a stopper, so that it is possible to prevent a constituent material of the aluminum layer from intruding into the gate insulating film. An end portion of the tantalum layer is transformed into tantalum oxide, which has an effect to lower damage at ion implantation to the gate insulating film in the formation of an LDD region.
    Type: Application
    Filed: March 21, 2002
    Publication date: July 25, 2002
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Etsuko Fujimoto, Takeshi Fukunaga, Hiroki Adachi, Hideto Ohnuma
  • Publication number: 20020096682
    Abstract: To provide a semiconductor device having a large aperture ratio, in which an auxiliary capacitance of a large capacity is provided in each pixel.
    Type: Application
    Filed: March 5, 2002
    Publication date: July 25, 2002
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hisashi Ohtani, Etsuko Fujimoto
  • Patent number: 6399960
    Abstract: The invention is to provide a high-productivity method for fabricating a TFT device having different LDD structures on one and the same substrate, and the TFT device. Specifically, the invention provides a novel TFT structure, and a high-productivity method for fabricating it. A Ta film or a Ta-based film having good heat resistance is used for forming interconnections, and the interconnections are covered with a protective film. The interconnections can be subjected to heat treatment at high temperatures (400 to 700° C.), and, in addition, the protective film serves as an etching stopper. In the peripheral driving circuit portion in the device, TFTs having an LDD structure are disposed in a self-aligned process in which is used side walls 126 and 127; while in the pixel matrix portion therein, TFTs having an LDD structure are disposed in a non-self-aligned process in which is used an insulator 125.
    Type: Grant
    Filed: July 14, 1999
    Date of Patent: June 4, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Etsuko Fujimoto, Atsuo Isobe, Toru Takayama, Kunihiko Fukuchi
  • Patent number: 6380561
    Abstract: To provide a semiconductor device having a large aperture ratio, in which an auxiliary capacitance of a large capacity is provided in each pixel. Capacitance wiring 102 comprising a tantalum film is formed on a substrate 101 having an insulating surface, and a tantalum oxide film 103 is formed by heat oxidation thereof. An active layer 104 comprising a semiconductor thin film is formed, and an auxiliary capacitance comprising the structure obtained by sandwiching the tantalum oxide film 103 with a part of the active layer 104 and the capacitance wiring 102 is formed. The active layer 104 functions as an active layer of a top-gate TFT.
    Type: Grant
    Filed: April 13, 1999
    Date of Patent: April 30, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Etsuko Fujimoto
  • Patent number: 6369410
    Abstract: A TFT using an aluminum material for a gate electrode is manufactured at a high yield factor. The gate electrode provided over an active layer and a gate insulating film is constituted by a lamination film of a tantalum layer and an aluminum layer. In this structure, the tantalum layer functions as a stopper, so that it is possible to prevent a constituent material of the aluminum layer from intruding into the gate insulating film. An end portion of the tantalum layer is transformed into tantalum oxide, which has an effect to lower damage at ion implantation to the gate insulating film in the formation of an LDD region.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: April 9, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Etsuko Fujimoto, Takeshi Fukunaga, Hiroki Adachi, Hideto Ohnuma
  • Publication number: 20020028544
    Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.
    Type: Application
    Filed: July 30, 2001
    Publication date: March 7, 2002
    Inventors: Etsuko Fujimoto, Satoshi Murakami, Shunpei Yamazaki, Shingo Eguchi
  • Publication number: 20020011597
    Abstract: There is provided a light emitting device including a TFT having a high driving capacity (on current) and high reliability in a driver circuit and a TFT in which an off current is reduced in a pixel portion. In manufacturing the TFTs, after the TFT having an LDD region is formed, a part of a gate electrode is etched to form the TFT having GOLD region. Thus, the TFTs having required functions can be easily formed in the driver circuit and the pixel portion, respectively, on the same substrate.
    Type: Application
    Filed: July 27, 2001
    Publication date: January 31, 2002
    Inventors: Etsuko Fujimoto, Satoshi Murakami, Kazutaka Inukai
  • Patent number: 6144082
    Abstract: A semiconductor device and a process for production thereof, said semiconductor device having a new electrode structure which has a low resistivity and withstands heat treatment at 400.degree. C. and above. Heat treatment at a high temperature (400-700.degree. C.) is possible because the wiring is made of Ta film or Ta-based film having high heat resistance. This heat treatment permits the gettering of metal element in crystalline silicon film. Since this heat treatment is lower than the temperature which the gate wiring (0.1-5 .mu.m wide) withstands and the gate wiring is protected with a protective film, the gate wiring retains its low resistance.
    Type: Grant
    Filed: July 14, 1999
    Date of Patent: November 7, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Etsuko Fujimoto, Atsuo Isobe, Toru Takayama, Kunihiko Fukuchi
  • Patent number: 6140166
    Abstract: A method for manufacturing a semiconductor, comprising crystallizing an amorphous silicon film formed on a substrate by employing lateral growth method using a catalyst element which accelerates the crystallization, wherein the duration of annealing accounts for 90% or more but less than 100% of the time for crystallization of the amorphous silicon film under the condition that no catalyst element is used.
    Type: Grant
    Filed: December 24, 1997
    Date of Patent: October 31, 2000
    Assignee: Semicondutor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Tamae Takano, Taketomi Asami, Etsuko Fujimoto
  • Patent number: 6091115
    Abstract: A semiconductor device having a CMOS structure comprising N-channel type and P-channel type insulated gate semiconductor devices combined in a complementary manner, wherein the threshold voltage of the insulated gate semiconductor devices is controlled by using the difference in work function between the gate electrode and the active layer. The present semiconductor device has excellent uniformity and reproducibility.
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: July 18, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Etsuko Fujimoto