Patents by Inventor Etsuo Morita

Etsuo Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20010048114
    Abstract: There are provided a semiconductor substrate and a semiconductor laser using the semiconductor substrate which promises smooth and optically excellent cleaved surfaces and is suitable for fabricating semiconductor lasers using nitride III-V compound semiconductors. Using a semiconductor substrate, such as GaN substrate, having a major surface substantially normal to a {0001}-oriented face, e.g. {01-10}-oriented face or {11-20}-oriented face, or offset within ±5° from these faces, nitride III-V compound semiconductor layers are epitaxially grown on the substrate to form a laser structure. To make cavity edges, the GaN substrate is cleaved together with the overlying III-V compound semiconductor layers along high-cleavable {0001}-oriented faces.
    Type: Application
    Filed: June 2, 1998
    Publication date: December 6, 2001
    Inventors: ETSUO MORITA, MASOA IKEDA, HIROJI KAWAI
  • Publication number: 20010020440
    Abstract: A crystal substrate and a crystal film of a III-V compound of the nitride system which have no defects in the surfaces. A method of manufacturing a crystal of a III-V compound of the nitride system, and a method of manufacturing a device. A base crystal layer is formed over a basal body. After etching the base crystal layer using a first mask pattern, an intermediate crystal layer is formed. After etching the intermediate crystal layer using a second mask pattern, a top crystal layer is formed. The crystal growth of the intermediate crystal layer starts at the walls of grooves formed by etching in the base crystal layer. This reduces the possibility that dislocations develop into the intermediate crystal layer. No dislocations occurring above the first mask pattern propagate through the top crystal layer since the dislocations are removed by etching using the second mask pattern.
    Type: Application
    Filed: November 30, 2000
    Publication date: September 13, 2001
    Inventor: Etsuo Morita
  • Publication number: 20010010941
    Abstract: To improve crystallographic property of a nitride III-V compound semiconductor layer grown on a sapphire substrate, a plurality of recesses are made on a major surface of the sapphire substrate, and the nitride III-V compound semiconductor layer is grown thereon. At least a part of the inner surface of each recess makes an angle not less than 10 degrees with respect to the major surface of the sapphire substrate. The recesses are buried with nitride III-V compound semiconductor crystal having a higher Al composition ratio than the nitride III-V compound semiconductor layer, such as AlxGa1−xN crystal whose Al composition ratio x is 0.2 or more, for example. Each recess has a depth not less than 25 nm and a width not less than 30 nm. The recesses may be made either upon thermal cleaning of the sapphire substrate or by using lithography and etching, thermal etching, or the like.
    Type: Application
    Filed: February 28, 2001
    Publication date: August 2, 2001
    Inventor: Etsuo Morita
  • Publication number: 20010004488
    Abstract: A base crystal layer is formed on the surface of a basal body by growing, e.g., GaN comprising a III-V compound by MOCVD and then the base crystal layer 12 is etched. An intermediate crystal layer is formed by laterally growing GaN from windows formed in the base crystal layer by etching. In the intermediate crystal layer, an inner layer made of, e.g., AlGaN is formed. Then, the intermediate crystal layer is further etched and a top crystal layer is formed by laterally growing GaN from windows formed in the intermediate crystal layer by etching. An inner layer made of, e.g., AlGaN is formed in the top crystal layer. Development of dislocations is suppressed to some extent by the lateral growth when forming the intermediate crystal layer and the top crystal layer. Further, development of dislocations is suppressed by the inner layers.
    Type: Application
    Filed: December 18, 2000
    Publication date: June 21, 2001
    Applicant: Sony Corporation
    Inventor: Etsuo Morita
  • Publication number: 20010003019
    Abstract: A crystal substrate and a crystal film of a III-V compound of the nitride system which are manufactured easily and have few dislocations. A method of manufacturing a crystal for the manufacture thereof, and a method of manufacturing a device with the use thereof. On a basal body, formed in order are a base crystal layer of, for example, gallium nitride (GaN), a first mask pattern of, for example, silicon dioxide (SiO2), an intermediate crystal layer of, for example, gallium nitride, a second mask pattern of, for example, silicon dioxide, and a top crystal layer of, for example, gallium nitride. The first and second mask patterns have stripes arranged at least in one direction at unequally spaced intervals. The stripes are different in pitch from pattern to pattern. Thus, the mask patterns at least partly overlie one another in the direction of the thickness of the crystal layers.
    Type: Application
    Filed: November 30, 2000
    Publication date: June 7, 2001
    Applicant: Sony Corporation
    Inventor: Etsuo Morita
  • Patent number: 6232623
    Abstract: To improve crystallographic property of a nitride III-V compound semiconductor layer grown on a sapphire substrate, a plurality of recesses are made on a major surface of the sapphire substrate, and the nitride III-V compound semiconductor layer is grown thereon. At least a part of the inner surface of each recess makes an angle not less than 10 degrees with respect to the major surface of the sapphire substrate. The recesses are buried with nitride III-V compound semiconductor crystal having a higher Al composition ratio than the nitride III-V compound semiconductor layer, such as AlxGa1−xN crystal whose Al composition ratio x is 0.2 or more, for example. Each recess has a depth not less than 25 nm and a width not less than 30 nm. The recesses may be made either upon thermal cleaning of the sapphire substrate or by using lithography and etching, thermal etching, or the like.
    Type: Grant
    Filed: June 17, 1999
    Date of Patent: May 15, 2001
    Assignee: Sony Corporation
    Inventor: Etsuo Morita
  • Patent number: 6121636
    Abstract: A semiconductor light emitting device is provided, which does not deteriorate in luminance, maintains a high reliability, permits more free choice of an adhesive, and promises effective extraction of light to the exterior even when it is bonded to a lead frame or other support with the adhesive in practical use. In a GaN light emitting diode, GaN compound semiconductor layers are stacked sequentially on a front surface of a sapphire substrate to form a light emitting diode structure, and a reflective film is formed on a rear surface. Alternatively, the GaN compound semiconductor layers forming the light emitting diode structure are selectively removed by etching to define an inverted mesa-shaped end surface, and the reflective film is formed on the end surface. Both the p-side electrode and the n-side electrode are formed on a common side of the substrate where the GaN compound semiconductor layers are formed.
    Type: Grant
    Filed: May 5, 1998
    Date of Patent: September 19, 2000
    Assignees: Sony Corporation, Sony Chemicals Corporation
    Inventors: Etsuo Morita, Hiroji Kawai
  • Patent number: 6107162
    Abstract: A semiconductor device such as a semiconductor layer is formed of a compound semiconductor layer of III-V group such as GaN. In the case where the substrate has not any planes that are easy to cleave which coincides with an easy-to-cleave plane of a semiconductor layer grown on the substrate or the substrate easily succumbs to cleavage, then the semiconductor layer together with the substrate can be broken into chips in an easy-to-cleave plane. The cleaved surface of the semiconductor layer can be positively formed as an optically superior surface. A compound semiconductor layer 2 containing at least one of the elements {Ga, Al, In} and N is formed on the substrate 1. This compound semiconductor layer 2 has a pair of facets of {11-20} plane substantially perpendicular to the substrate 1.
    Type: Grant
    Filed: April 14, 1998
    Date of Patent: August 22, 2000
    Assignee: Sony Corporation
    Inventors: Etsuo Morita, Hiroji Kawai
  • Patent number: 5828086
    Abstract: A semiconductor light emitting device ccomprises a first cladding layer, an active layer and a second cladding layer which are stacked on a semiconductor substrate. At least a part of the first cladding layer and the second cladding layer has a superlattice structure comprising II-VI compound semiconductor. Another semiconductor light emitting device comprises a first cladding layer, a first guide layer, an active layer, a second guide layer and a second cladding layer which are stacked on a semiconductor substrate. At least a part of the first cladding layer, the first guide layer, the second cladding layer and the second guide layer has a superlattice structure. Still anothr semiconductor light emitting device comprises a defect decomposing layer, a defect blocking layer, a first cladding layer, an active layer, a second cladding layer which are stacked on a semiconductor substrate. The defect decomposing layer and the defect blocking layer comprise a superlattice structure.
    Type: Grant
    Filed: March 24, 1997
    Date of Patent: October 27, 1998
    Assignee: Sony Corporation
    Inventors: Akira Ishibashi, Satoshi Matsumoto, Masaharu Nagai, Satoshi Ito, Shigetaka Tomiya, Kazushi Nakano, Etsuo Morita
  • Patent number: 5821568
    Abstract: A semiconductor device such as a semiconductor layer is formed of a compound semiconductor layer of III-V group such as GaN. In the case where the substrate has not any planes that are easy to cleave which coincides with an easy-to-cleave plane of a semiconductor layer grown on the substrate or the substrate easily succumbs to cleavage, then the semiconductor layer together with the substrate can be broken into chips in an easy-to-cleave plane. The cleaved surface of the semiconductor layer can be positively formed as an optically superior surface. A compound semiconductor layer 2 containing at least one of the elements {Ga, Al, In} and N is formed on the substrate 1. This compound semiconductor layer 2 has a pair of facets of {11-20} plane substantially perpendicular to the substrate 1.
    Type: Grant
    Filed: December 18, 1996
    Date of Patent: October 13, 1998
    Assignee: Sony Corporation
    Inventors: Etsuo Morita, Hiroji Kawai
  • Patent number: 5753966
    Abstract: A semiconductor light emitting device is prepared by the steps of forming a semiconductor layer 2 having a laminated structure containing at least a first cladding layer 6, a light emitting layer 7, and a second cladding layer 8 on a substrate 1 having {11-20} plane (plane a) as the main plane; and breaking integrally the semiconductor layer 2 and the substrate 1 under a heating condition to form a pair of facets on the above described substrate due to the plane which was cleaved in {1-102} plane (plane r) and at the same time, to form a pair of facets 3 extending along the above described pair of facets of the substrate 1 on the semiconductor layer 2.
    Type: Grant
    Filed: December 19, 1996
    Date of Patent: May 19, 1998
    Assignee: Sony Corporation
    Inventors: Etsuo Morita, Hiroji Kawai
  • Patent number: 5705421
    Abstract: A SOI substrate fabricating method comprises the steps of: making a first etch-stop layer on a silicon substrate; polishing the surface of the first etch-stop layer; making a silicon buffer layer on the polished surface of the first etch-stop layer; making a silicon layer on the silicon buffer layer; making an insulating layer on the silicon layer; bonding one of major surfaces of a support substrate onto the insulating layer; and removing the silicon substrate, the first etch-stop layer and the silicon buffer layer and maintaining the insulating layer and the silicon layer on the one surface of the support substrate.
    Type: Grant
    Filed: November 22, 1995
    Date of Patent: January 6, 1998
    Assignees: Sony Corporation, Mitsubishi Materials Corporation, Mitsubishi Materials Silicon Corporation
    Inventors: Takeshi Matsushita, Etsuo Morita, Tsuneo Nakajima, Hiroyuki Hasegawa, Takayuki Shingyouji
  • Patent number: 5665977
    Abstract: A semiconductor light emitting device comprises a first cladding layer, an active layer and a second cladding layer which are stacked on a semiconductor substrate. At least a part of the first cladding layer and the second cladding layer has a superlattice structure comprising II-VI compound semiconductor. Another semiconductor light emitting device comprises a first cladding layer, a first guide layer, an active layer, a second guide layer and a second cladding layer which are stacked on semiconductor substrate. At least a part of the first cladding layer, the first guide layer, the second cladding layer and the second guide layer has a superlattice structure. Still another semiconductor light emitting device comprises a defect decomposing layer, a defect blocking layer, first cladding layer, an active layer, a second cladding layer which are stacked on a semiconductor substrate. The defect decomposing layer and the defect blocking layer comprise a superlattice structure.
    Type: Grant
    Filed: August 2, 1996
    Date of Patent: September 9, 1997
    Assignee: Sony Corporation
    Inventors: Akira Ishibashi, Satoshi Matsumoto, Masaharu Nagai, Satoshi Ito, Shigetaka Tomiya, Kazushi Nakano, Etsuo Morita
  • Patent number: 5418374
    Abstract: A ridge or groove is formed on a major surface of a semiconductor substrate which is formed on a first electrode and whose major surface having a ridge or groove is slanted to a <110> crystal axis direction from a {001} crystal plane. A first semiconductor layer is formed on the semiconductor substrate, then a semiconductor function layer deviating from a {111} B crystal plane is formed on the first semiconductor layer, then a second semiconductor layer is formed on the semiconductor function layer and then a second electrode is formed on the second semiconductor layer. The ridge or groove extends to the <110> crystal axis direction, and at least one of the first semiconductor layer, the semiconductor function layer and the second semiconductor layer includes phosphorus.
    Type: Grant
    Filed: June 2, 1993
    Date of Patent: May 23, 1995
    Assignee: Sony Corporation
    Inventors: Etsuo Morita, Shigetaka Tomiya, Tadashi Yamamoto, Akira Ishibashi