Abstract: Early exit of a loop is performed. A determination is made as to whether a loop within computer code reaches a fixed point of processing, which is predefined. Based on determining that the loop reaches the fixed point of processing, at least one indication is included in the loop to perform an early exit of the loop prior to a last iteration of the loop.

Abstract: Aspects include modeling data cache utilization for each loop in a loop nest; estimating total data cache lines fetched in one iteration of the loop; and determining the possibility of data cache reuse across loop iterations using data cache lines fetched and associativity constraints. Aspects also include estimating, for memory reference pairs, reuse by one reference of data cache line fetched by another; estimating total number of cache misses for all iterations of the loop; and estimating total number of cache misses of a reference for iterations of a next outer loop as equal to total cache misses for an entire inner loop. Aspects further include estimating memory cost of a loop unroll and jam transformation, without performing the transformation; and extending a data cache model to estimate best unroll-and-jam factors for the loop nest, capable of minimizing total cache misses incurred by the memory references in the loop body.

Abstract: Aspects include modeling data cache utilization for each loop in a loop nest; estimating total data cache lines fetched in one iteration of the loop; and determining the possibility of data cache reuse across loop iterations using data cache lines fetched and associativity constraints. Aspects also include estimating, for memory reference pairs, reuse by one reference of data cache line fetched by another; estimating total number of cache misses for all iterations of the loop; and estimating total number of cache misses of a reference for iterations of a next outer loop as equal to total cache misses for an entire inner loop. Aspects further include estimating memory cost of a loop unroll and jam transformation, without performing the transformation; and extending a data cache model to estimate best unroll-and-jam factors for the loop nest, capable of minimizing total cache misses incurred by the memory references in the loop body.

Abstract: Aspects include executing a first phase that includes injecting instrumentation into program code in response to identifying an inner conditional check in the program code and running the instrumented program with a representative workload. The injecting includes duplicating the inner conditional check and placing a duplicate of the inner conditional check before a respective original nested conditional check in the program code to create an instrumented program. The instrumented program includes a plurality of basic blocks including original basic blocks and a newly added basic block that includes the duplicate of the inner conditional check. The method also includes executing a second phase that includes collecting execution frequency values from counters associated with the basic blocks to form metadata used to make optimization decisions for the program code.

Abstract: Allocating distributed data structures and managing allocation of a symmetric heap can include defining, using a processor, the symmetric heap. The symmetric heap includes a symmetric partition for each process of a partitioned global address space (PGAS) system. Each symmetric partition of the symmetric heap begins at a same starting virtual memory address and has a same global symmetric break. One process of a plurality of processes of the PGAS system is configured as an allocator process that controls allocation of blocks of memory for each symmetric partition of the symmetric heap. Using the processor executing the allocator process, isomorphic fragmentation among the symmetric partitions of the symmetric heap is maintained.

Abstract: Methods, systems, and computer program products for hardware device selection in a computing environment are provided. Aspects include receiving, by a processor, a request to execute a programming code, wherein the processor is operating in a hybrid computing environment comprising a plurality of hardware devices. A performance model associated with the programming code is obtained by the processor. Runtime data associated with the programming code is obtained by the processor. The runtime data is fed in to the performance model to determine an execution cost for executing the programming code on each of the plurality of hardware devices and a target hardware device is selected from the plurality of hardware devices based on the execution costs.

Abstract: A method, computer system, and a computer program product for high-speed data compression is provided. The present invention may include receiving an input stream. The present invention may include selecting a header based on the received input stream, wherein the header includes a base, a scheme and a delta count. The present invention may include determining whether there are any remaining values in an uncompressed input stream. The present invention may include reading a first next value from the input stream. The present invention may include determining whether the read first next value is representable with a current base scheme. The present invention may include calculating the delta count based on determining that the read first next value is representable with the current base scheme. The present invention may include writing the calculated delta count to the selected header. The present invention may include incrementing the written delta count.

Abstract: Methods, systems, and computer program products for hardware device selection in a computing environment are provided. Aspects include receiving, by a processor, a request to execute a programming code, wherein the processor is operating in a hybrid computing environment comprising a plurality of hardware devices. A performance model associated with the programming code is obtained by the processor. Runtime data associated with the programming code is obtained by the processor. The runtime data is fed in to the performance model to determine an execution cost for executing the programming code on each of the plurality of hardware devices and a target hardware device is selected from the plurality of hardware devices based on the execution costs.

Abstract: Embodiments of the present invention facilitate pruning a dependence graph for a loop in a computer program. An example computer-implemented method includes determining, by a compiler, a source and a sink of a dependence in the dependence graph. The method further includes determining, by the compiler, a source symbolic expression for the source, and a sink symbolic expression for the sink. The method further includes constructing, by the compiler, a difference expression using the source symbolic expression and the sink symbolic expression. The method further includes checking, by the compiler, if the difference expression is indicative of a memory overlap between the source and the sink. The method further includes, in response to the difference expression being indicative of no overlap, removing the dependence from the dependence graph, and generating object code for the computer program based on the dependence graph.

Abstract: A method, computer system, and a computer program product for high-speed data compression is provided. The present invention may include receiving an input stream. The present invention may include selecting a header based on the received input stream, wherein the header includes a base, a scheme and a delta count. The present invention may include determining whether there are any remaining values in an uncompressed input stream. The present invention may include reading a first next value from the input stream. The present invention may include determining whether the read first next value is representable with a current base scheme. The present invention may include calculating the delta count based on determining that the read first next value is representable with the current base scheme. The present invention may include writing the calculated delta count to the selected header. The present invention may include incrementing the written delta count.

Abstract: A method, computer system, and a computer program product for high-speed data compression is provided. The present invention may include receiving an input stream. The present invention may include selecting a header based on the received input stream, wherein the header includes a base, a scheme and a delta count. The present invention may include determining whether there are any remaining values in an uncompressed input stream. The present invention may include reading a first next value from the input stream. The present invention may include determining whether the read first next value is representable with a current base scheme. The present invention may include calculating the delta count based on determining that the read first next value is representable with the current base scheme. The present invention may include writing the calculated delta count to the selected header. The present invention may include incrementing the written delta count.

Abstract: Embodiments of the present invention facilitate pruning a dependence graph for a loop in a computer program. An example computer-implemented method includes determining, by a compiler, a source and a sink of a dependence in the dependence graph. The method further includes determining, by the compiler, a source symbolic expression for the source, and a sink symbolic expression for the sink. The method further includes constructing, by the compiler, a difference expression using the source symbolic expression and the sink symbolic expression. The method further includes checking, by the compiler, if the difference expression is indicative of a memory overlap between the source and the sink. The method further includes, in response to the difference expression being indicative of no overlap, removing the dependence from the dependence graph, and generating object code for the computer program based on the dependence graph.

Abstract: The present disclosure relates to minimizing the execution time of compute workloads in a distributed computing system. An example method generally includes receiving, from each of a plurality of server clusters, an estimated completion time and cost information predicted to be consumed in processing the compute workload. A workload manager compares the received estimates to a completion time and threshold cost criteria. Upon determining that the estimated completion time and cost information from any of the plurality of server clusters does not satisfy the completion time and threshold cost criteria, the workload manager partitions the compute workload into a plurality of segments, requests estimated completion time and cost information from the plurality of server clusters for each of the plurality of segments, and selects a cluster to process each segment of the compute workload based on the estimated completion time and cost reported for each segment.

Abstract: A method, computer system, and a computer program product for high-speed data compression is provided. The present invention may include receiving an input stream. The present invention may include selecting a header based on the received input stream, wherein the header includes a base, a scheme and a delta count. The present invention may include determining whether there are any remaining values in an uncompressed input stream. The present invention may include reading a first next value from the input stream. The present invention may include determining whether the read first next value is representable with a current base scheme. The present invention may include calculating the delta count based on determining that the read first next value is representable with the current base scheme. The present invention may include writing the calculated delta count to the selected header. The present invention may include incrementing the written delta count.

Abstract: Allocating distributed data structures and managing allocation of a symmetric heap can include defining, using a processor, the symmetric heap. The symmetric heap includes a symmetric partition for each process of a partitioned global address space (PGAS) system. Each symmetric partition of the symmetric heap begins at a same starting virtual memory address and has a same global symmetric break. One process of a plurality of processes of the PGAS system is configured as an allocator process that controls allocation of blocks of memory for each symmetric partition of the symmetric heap. Using the processor executing the allocator process, isomorphic fragmentation among the symmetric partitions of the symmetric heap is maintained.

Abstract: Aspects of the present invention include a method which includes a processor providing a debug extension library; providing a common debug interface and at least two common debug interface implementations, a first one of the common debug interface implementations being dedicated to a native debugger of an interpreted language computer program, a second one of the common debug interface implementations being dedicated to a native debugger of a compiled language computer program, wherein an application contains a first portion written in an interpreted programming language and a second portion written in a compiled programming language; and responding to a user command provided through a debug script program to debug the application by commanding one of the native debugger of an interpreted language computer program or the native debugger of a compiled language computer program through the corresponding dedicated common debug interface implementation.

Abstract: In an approach to problem determination for cooperating web services, a computing device executes a debug script. The computing device discovers one or more web services based on a web service discovery mechanism. The computing device connects, by the debug daemon, with a debug probe to set a breakpoint on a web service. The computing device receives a file containing connection parameters. The computing device initiates a debug session with the web service using a designated connection channel. The computing device invokes a breakpoint handler function for the web service. The computing device sends commands to the debug probe, which forwards the debug commands to the web service. The computing device closes the debug session with the web service when the breakpoint handler function has run to completion.

Abstract: Allocating distributed data structures and managing allocation of a symmetric heap can include defining, using a processor, the symmetric heap. The symmetric heap includes a symmetric partition for each process of a partitioned global address space (PGAS) system. Each symmetric partition of the symmetric heap begins at a same starting virtual memory address and has a same global symmetric break. One process of a plurality of processes of the PGAS system is configured as an allocator process that controls allocation of blocks of memory for each symmetric partition of the symmetric heap. Using the processor executing the allocator process, isomorphic fragmentation among the symmetric partitions of the symmetric heap is maintained.

Abstract: Allocating distributed data structures and managing allocation of a symmetric heap can include defining, using a processor, the symmetric heap. The symmetric heap includes a symmetric partition for each process of a partitioned global address space (PGAS) system. Each symmetric partition of the symmetric heap begins at a same starting virtual memory address and has a same global symmetric break. One process of a plurality of processes of the PGAS system is configured as an allocator process that controls allocation of blocks of memory for each symmetric partition of the symmetric heap. Using the processor executing the allocator process, isomorphic fragmentation among the symmetric partitions of the symmetric heap is maintained.

Abstract: Aspects of the present invention include a method which includes a processor providing a debug extension library; providing a common debug interface and at least two common debug interface implementations, a first one of the common debug interface implementations being dedicated to a native debugger of an interpreted language computer program, a second one of the common debug interface implementations being dedicated to a native debugger of a compiled language computer program, wherein an application contains a first portion written in an interpreted programming language and a second portion written in a compiled programming language; and responding to a user command provided through a debug script program to debug the application by commanding one of the native debugger of an interpreted language computer program or the native debugger of a compiled language computer program through the corresponding dedicated common debug interface implementation.