Patents by Inventor Ettore Tiotto
Ettore Tiotto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20180103088Abstract: The present disclosure relates to minimizing the execution time of compute workloads in a distributed computing system. An example method generally includes receiving, from each of a plurality of server clusters, an estimated completion time and cost information predicted to be consumed in processing the compute workload. A workload manager compares the received estimates to a completion time and threshold cost criteria. Upon determining that the estimated completion time and cost information from any of the plurality of server clusters does not satisfy the completion time and threshold cost criteria, the workload manager partitions the compute workload into a plurality of segments, requests estimated completion time and cost information from the plurality of server clusters for each of the plurality of segments, and selects a cluster to process each segment of the compute workload based on the estimated completion time and cost reported for each segment.Type: ApplicationFiled: October 11, 2016Publication date: April 12, 2018Inventors: Robert J. BLAINEY, Daniel G. FOISY, Heng KUANG, Taylor J. LLOYD, Ettore TIOTTO
-
Patent number: 9898384Abstract: In an approach to problem determination for cooperating web services, a computing device executes a debug script. The computing device discovers one or more web services based on a web service discovery mechanism. The computing device connects, by the debug daemon, with a debug probe to set a breakpoint on a web service. The computing device receives a file containing connection parameters. The computing device initiates a debug session with the web service using a designated connection channel. The computing device invokes a breakpoint handler function for the web service. The computing device sends commands to the debug probe, which forwards the debug commands to the web service. The computing device closes the debug session with the web service when the breakpoint handler function has run to completion.Type: GrantFiled: March 18, 2016Date of Patent: February 20, 2018Assignee: International Business Machines CorporationInventors: Eugene W. Chan, Yingcong Guan, John R. MacMillan, Ettore Tiotto, Trong Truong
-
Publication number: 20170270027Abstract: In an approach to problem determination for cooperating web services, a computing device executes a debug script. The computing device discovers one or more web services based on a web service discovery mechanism. The computing device connects, by the debug daemon, with a debug probe to set a breakpoint on a web service. The computing device receives a file containing connection parameters. The computing device initiates a debug session with the web service using a designated connection channel. The computing device invokes a breakpoint handler function for the web service. The computing device sends commands to the debug probe, which forwards the debug commands to the web service. The computing device closes the debug session with the web service when the breakpoint handler function has run to completion.Type: ApplicationFiled: March 18, 2016Publication date: September 21, 2017Inventors: Eugene W. Chan, Yingcong Guan, John R. MacMillan, Ettore Tiotto, Trong Truong
-
Publication number: 20170270023Abstract: In an approach to problem determination for cooperating web services, a computing device executes a debug script. The computing device discovers one or more web services based on a web service discovery mechanism. The computing device connects, by the debug daemon, with a debug probe to set a breakpoint on a web service. The computing device receives a file containing connection parameters. The computing device initiates a debug session with the web service using a designated connection channel. The computing device invokes a breakpoint handler function for the web service. The computing device sends commands to the debug probe, which forwards the debug commands to the web service. The computing device closes the debug session with the web service when the breakpoint handler function has run to completion.Type: ApplicationFiled: June 16, 2016Publication date: September 21, 2017Inventors: Eugene W. Chan, Yingcong Guan, John R. MacMillan, Ettore Tiotto, Trong Truong
-
Patent number: 9038045Abstract: Control flow information and data flow information associated with a program containing a upc_forall loop are built. A shared reference map data structure using the control flow information and the data flow information is created. All local shared accesses are hashed to facilitate a constant access stride after being rewritten. All local shared references in a hash entry having a longest list are privatized. The upc_forall loop is rewritten into a for loop. Responsive to a determination that an unprocessed upc_forall loop does not exist, dead store elimination is run. The control flow information and the data flow information associated with the program containing the for loop is rebuilt.Type: GrantFiled: November 15, 2011Date of Patent: May 19, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yaoqing Gao, Liangxiao Hu, Raul Esteban Silvera, Ettore Tiotto
-
Patent number: 8990791Abstract: Partitioned global address space (PGAS) programming language source code is retrieved by an executed PGAS compiler. At least one shared memory array access indexed by an affine expression that includes a distinct thread identifier that is constant and different for each of a group of program execution threads targeted to execute the PGAS source code is identified within the PGAS source code. It is determined whether the at least one shared memory array access results in a local shared memory access by all of the group of program execution threads for all references to the at least one shared memory array access during execution of a compiled executable of the PGAS source code. A direct memory access executable code is generated for each shared memory array access determined to result in the local shared memory access by all of the group of program execution threads.Type: GrantFiled: July 29, 2011Date of Patent: March 24, 2015Assignee: International Business Machines CorporationInventors: Salem Derisavi, Ettore Tiotto
-
Patent number: 8930927Abstract: A compiler generated static analysis of potential aliasing violations in a portion of code that is not in the current program view of the analysis. Source code in a current program view of the program code is processed to collect symbol definitions. The possible destinations of each symbol definition are computed. The set of symbol definitions in the current program view of the code that are accessible to the portion of the program code outside the current program view is evaluated. Each symbol definition is diagnosed based on the type of the symbol defined and the symbols which may be pointed-to by the symbol definitions.Type: GrantFiled: December 18, 2008Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Christopher Eugene Bowler, Sean Douglas Perry, Ettore Tiotto
-
Publication number: 20140372725Abstract: Allocating distributed data structures and managing allocation of a symmetric heap can include defining, using a processor, the symmetric heap. The symmetric heap includes a symmetric partition for each process of a partitioned global address space (PGAS) system. Each symmetric partition of the symmetric heap begins at a same starting virtual memory address and has a same global symmetric break. One process of a plurality of processes of the PGAS system is configured as an allocator process that controls allocation of blocks of memory for each symmetric partition of the symmetric heap. Using the processor executing the allocator process, isomorphic fragmentation among the symmetric partitions of the symmetric heap is maintained.Type: ApplicationFiled: June 14, 2013Publication date: December 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gheorghe Almasi, Barnaby Dalton, Ilie G. Tanase, Ettore Tiotto
-
Publication number: 20140372724Abstract: Allocating distributed data structures and managing allocation of a symmetric heap can include defining, using a processor, the symmetric heap. The symmetric heap includes a symmetric partition for each process of a partitioned global address space (PGAS) system. Each symmetric partition of the symmetric heap begins at a same starting virtual memory address and has a same global symmetric break. One process of a plurality of processes of the PGAS system is configured as an allocator process that controls allocation of blocks of memory for each symmetric partition of the symmetric heap. Using the processor executing the allocator process, isomorphic fragmentation among the symmetric partitions of the symmetric heap is maintained.Type: ApplicationFiled: June 13, 2013Publication date: December 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gheorghe Almasi, Barnaby Dalton, Ilie G. Tanase, Ettore Tiotto
-
Patent number: 8856763Abstract: An embodiment is directed to determining, by a compiler, that a call to a named barrier is matched across all of a plurality of threads, and based at least in part on determining that the call to the named barrier is matched across all of the plurality of threads, replacing, by the compiler, the named barrier with an unnamed barrier.Type: GrantFiled: March 18, 2014Date of Patent: October 7, 2014Assignee: International Business Machines CorporationInventors: Yaxun Liu, Ilie G. Tanase, Ettore Tiotto
-
Patent number: 8839219Abstract: An illustrative embodiment of a computer-implemented process for shared data prefetching and coalescing optimization versions a loop containing one or more shared references into an optimized loop and an un-optimized loop, transforms the optimized loop into a set of loops, and stores shared access associated information of the loop using a prologue loop in the set of loops. The shared access associated information pertains to remote data and is collected using the prologue loop in absence of network communication and builds a hash table. An associated data structure is updated each time the hash table is entered, and is sorted to remove duplicate entries and create a reduced data structure. Patterns across entries of the reduced data structure are identified and entries are coalesced. Data associated with a coalesced entry is pre-fetched using a single communication and a local buffer is populated with the fetched data for reuse.Type: GrantFiled: October 24, 2012Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Michail Alvanos, Ettore Tiotto
-
Patent number: 8839218Abstract: A computer implemented method, apparatus, and computer usable program code for facilitating debugging of source code. A set of indirect memory references is identified in the source code and points-to records are generated for the source code. The set of indirect memory references are validated using the points-to records and an aliasing rule to identify zero or more indirect memory references having a potential aliasing problem. In a case in which the zero or more indirect memory references comprise at least one indirect memory reference, the at least one indirect memory reference is in the set of indirect memory references. Responsive to a determination that the zero or more indirect memory references comprise at least one indirect memory reference, a report is generated identifying at least one location in the source code associated with the at least one indirect memory reference. The report is stored.Type: GrantFiled: June 4, 2007Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Christopher E. Bowler, Raymond Ying Chau Mak, Sean Douglas Perry, Ettore Tiotto, Enrique Varillas
-
Patent number: 8839216Abstract: An embodiment is directed to determining, by a compiler, that a call to a named barrier is matched across all of a plurality of threads, and based at least in part on determining that the call to the named barrier is matched across all of the plurality of threads, replacing, by the compiler, the named barrier with an unnamed barrier.Type: GrantFiled: November 7, 2012Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Yaxun Liu, Ilie G. Tanase, Ettore Tiotto
-
Patent number: 8819346Abstract: A computer implemented method analyzes shared memory accesses during execution of an application program. The method includes instrumenting events of shared memory accesses in the application program, where the application program is to be executed on a target configuration having p nodes; executing the application program using p1 processing nodes, where p1 is less than p and satisfies a constraint. For accesses made by the executing application program, the method determines a target thread and maps determined target threads to either a remote node or a local node corresponding to a remote memory access and to a local memory access, respectively. Also disclosed is a computer-readable storage medium that stores a program of executable instructions that implements the method, and a data processing system. The invention can be implemented using a language such as Unified Parallel C (UPC) directed to a partitioned global address space (PGAS) paradigm.Type: GrantFiled: March 9, 2012Date of Patent: August 26, 2014Assignee: International Business Machines CorporationInventors: Guojing Cong, Ettore Tiotto, Hui-Fang Wen
-
Publication number: 20140196018Abstract: An embodiment is directed to determining, by a compiler, that a call to a named barrier is matched across all of a plurality of threads, and based at least in part on determining that the call to the named barrier is matched across all of the plurality of threads, replacing, by the compiler, the named barrier with an unnamed barrier.Type: ApplicationFiled: March 18, 2014Publication date: July 10, 2014Applicant: International Business Machines CorporationInventors: Yaxun Liu, Ilie G. Tanase, Ettore Tiotto
-
Publication number: 20140115276Abstract: Partitioned global address space (PGAS) programming language source code is retrieved by an executed PGAS compiler. At least one shared memory array access indexed by an affine expression that includes a distinct thread identifier that is constant and different for each of a group of program execution threads targeted to execute the PGAS source code is identified within the PGAS source code. It is determined whether the at least one shared memory array access results in a local shared memory access by all of the group of program execution threads for all references to the at least one shared memory array access during execution of a compiled executable of the PGAS source code. A direct memory access executable code is generated for each shared memory array access determined to result in the local shared memory access by all of the group of program execution threads.Type: ApplicationFiled: July 29, 2011Publication date: April 24, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Salem Derisavi, Ettore Tiotto
-
Publication number: 20130238862Abstract: A computer implemented method analyzes shared memory accesses during execution of an application program. The method includes instrumenting events of shared memory accesses in the application program, where the application program is to be executed on a target configuration having p nodes; executing the application program using p1 processing nodes, where p1 is less than p and satisfies a constraint. For accesses made by the executing application program, the method determines a target thread and maps determined target threads to either a remote node or a local node corresponding to a remote memory access and to a local memory access, respectively. Also disclosed is a computer-readable storage medium that stores a program of executable instructions that implements the method, and a data processing system. The invention can be implemented using a language such as Unified Parallel C (UPC) directed to a partitioned global address space (PGAS) paradigm.Type: ApplicationFiled: March 9, 2012Publication date: September 12, 2013Applicant: International Business Machines CorporationInventors: Guojing Cong, Ettore Tiotto, Hui-Fang Wen
-
Patent number: 8527962Abstract: A method for promotion of a child procedure in a software application for a heterogeneous architecture, wherein the heterogeneous architecture comprises a first architecture type and a second architecture type, comprises inserting a parameter representing a parallel frame pointer to a parent procedure of the child procedure into the child procedure; and modifying a reference in the child procedure to a stack variable of the parent procedure to include an indirect access to the parent procedure via the parallel frame pointer.Type: GrantFiled: March 10, 2009Date of Patent: September 3, 2013Assignee: International Business Machines CorporationInventors: Raul Silvera, Ettore Tiotto, Guansong Zhang
-
Publication number: 20130125105Abstract: Control flow information and data flow information associated with a program containing a upc_forall loop are built. A shared reference map data structure using the control flow information and the data flow information is created. All local shared accesses are hashed to facilitate a constant access stride after being rewritten. All local shared references in a hash entry having a longest list are privatized. The upc_forall loop is rewritten into a for loop. Responsive to a determination that an unprocessed upc_forall loop does not exist, dead store elimination is run. The control flow information and the data flow information associated with the program containing the for loop is rebuilt.Type: ApplicationFiled: November 15, 2011Publication date: May 16, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yaoqing Gao, Liangxiao Hu, Raul Esteban Silvera, Ettore Tiotto
-
Publication number: 20100235811Abstract: A method for promotion of a child procedure in a software application for a heterogeneous architecture, wherein the heterogeneous architecture comprises a first architecture type and a second architecture type, comprises inserting a parameter representing a parallel frame pointer to a parent procedure of the child procedure into the child procedure; and modifying a reference in the child procedure to a stack variable of the parent procedure to include an indirect access to the parent procedure via the parallel frame pointer.Type: ApplicationFiled: March 10, 2009Publication date: September 16, 2010Applicant: International Business Machines CorporationInventors: Raul Silvera, Ettore Tiotto, Guansong Zhang