Abstract: A MOS architecture for reading rows of pixels in an area array imager. After initial setup, individual pixels are read one row at a time using one clock pulse per pixel.

Abstract: Two methods for suppressing the fixed pattern noise effects of a pixel reset switch by ensuring that the reset NMOS device operates in its linear region. The first approach uses a separate reset switch supply voltage, VRES, set to at least one threshold voltage below the sensing switch supply voltage, Vdd. The second approach uses a charge pump and level shifter to push the reset gate voltage at least one threshold voltage higher than a supply voltage common to both the reset and sense transistors.

Abstract: A monolithic optical detector for determining spectral content of an incident light includes at least a first and second well in a substrate, the second well formed proximate the first well. The first well is configured to be exposed to incident light and for generating a first photocurrent as a function of the incident light. The second well is configured to be shielded from the incident light and for generating a second photocurrent as a function of the incident light. Lastly, a processing and control unit, responsive to the first and second photocurrents, determines an indication of spectral content of the incident light. A method and device parameter controller are also disclosed.

Abstract: A monolithic optical detector for determining spectral content of an incident light includes at least a first and second well in a substrate, the second well formed proximate the first well. The first well is configured to be exposed to incident light and for generating a first photocurrent as a function of the incident light. The second well is configured to be shielded from the incident light and for generating a second photocurrent as a function of the incident light. Lastly, a processing and control unit, responsive to the first and second photocurrents, determines an indication of spectral content of the incident light. A method and device parameter controller are also disclosed.

Abstract: A technique for serially controlling an array of optical sensor chips over a pair of signal lines. After broadcasting an initializing reset command to all chips over serial lines, a determine-address command is broadcast to commence unique address determination. On subsequent clock signals, each chip locks its address into an on-board register. Following this process, each chip can be addressed individually. Subsequently, when each array chip is directed to read data out, the data is output to a single common bus line to the controller. Alternatively, individual chip outputs may be connected directly to the controller, or the outputs of odd and even chip pairs may be tied together for broadcast readout of all odd chips or all even chips.

Abstract: Driver circuitry (300) is disclosed, incorporating feedback circuitry (310) inter-coupled with reference circuitry (348) to equalize the voltage level of an output (328) with a reference voltage source (320) in the reference circuitry; where the driver circuitry comprises a first transistor (340) having a first terminal coupled to a voltage source (342), a second terminal coupled to an input (336), and a third terminal coupled to a resistor (344), a second transistor (338) having a first terminal coupled to ground (332), a second terminal coupled to an input (334), and a third terminal coupled to a resistor (346), a third transistor (318) having a first terminal coupled to the output, a second terminal (326) coupled jointly to the resistors, and a third terminal coupled to ground, and a resistor (330) coupling the output to a voltage source (306).

Abstract: An optical sensor array with zone-programmable gain and offset prior to A/D conversion for reducing quantization noise. The circuit comprises a register file which contains digital words for controlling gain and offset according to multi-pixel zones.

Abstract: A CMOS area array sensor with reduced fixed pattern noise. Device threshold voltage variations are minimied using a Sequential Correlated Double Sampling technique in a column circuitry.

Abstract: A driver circuit (12) having a controlled transition rate is provided. The driver circuit (12) includes a first device (56) operable to switch a supply voltage to load. A second device (54) is coupled to an input for the first device (56) in source follower arrangement. A third device (66), coupled to the input for first device (56) and an output for the second device (54), is operable to function as a Miller amplifier in conjunction with the first device (56). A fourth device (152) is coupled to an input of the second device (54). The fourth device (152) is operable to function as a Miller amplifier in conjunction with the first device (56) and the second device (54). A capacitor (68) is coupled between an output for the first device (56) and inputs for the third device (66) and the fourth device (152). The capacitor (68) is operable to function as a Miller capacitor to control transition rates at the output of the first device (56).

Abstract: An integrated circuit resistor (18) has a layout in which a first parasitic capacitance (26) exists between first portions of the resistor (18) and a first integrated circuit feature (34), and a second parasitic capacitance (28) exists between second portions of the resistor and a second integrated circuit feature (32). The resistor (18) may have, for example, a zigzag or serpentine configuration, with portions of each leg of the zigzag configuration overlying the first and second integrated circuit features (34,32). The first and second integrated circuit features (34,32) are configured to produce substantially canceling charges on the first and second parasitic capacitances (26,28). The resistor may be defined by a doped semiconductor material, such as a polysilicon layer. The resistor may be used in many applications, such as a feedback resistor of an optoelectronic current-to-voltage converter (12).

Abstract: A driver circuit (12) having a reduced propagation delay is provided. The driver circuit (12) includes a first device (56) having an input and operable to switch a supply voltage to a load (14). A second device (54) having an output coupled to the input of the first device (56), operable to turn on the first device upon receipt of a first signal. A third device (66) having an output coupled to the input of the first device (56), operable to turn off the first device upon receipt of a second signal. A kick start circuit (30) coupled to the input for the first device (56), the input for the second device (54), and the input for the third device (66), operable to generate a threshold voltage on the first device (56), the second device (54), and the third device (66). The kick start circuit (30) operable to produce a threshold voltage that is just below the voltage in which the first device (56), the second device (54), and the third device (66) turn on, or conduct.

Abstract: Managed integration optical sensor array (11) having an array block (12). The array block having a plurality of optical sensors (13), a switch control logic circuit (59) and a bit shift register (60). The switch control logic circuit (59) operating to control the integration periods of each optical sensor (13).

Abstract: Active integrator optical sensor (13) having a photodetector (56) and an active integrator circuit. The active integrator circuit having an operational amplifier (50), an integrating capacitor (51) an offset capacitor (54) and a store capacitor (52). The active integrator circuit operating to integrate the electrical signal from photodetector (56).

Abstract: Color optical sensor array (11) having a color optical sensor (13) with each color optical sensor (13) having a color photodetector (56) and an active integrator circuit. The active integrator circuit having an operational amplifier (50) and an integrating capacitor (51), the active integrator circuit operating to integrate and normalize the electrical signal from color photodetector (56).

Abstract: An integrated circuit resistor (18) has a layout in which a first parasitic capacitance (26) exists between first portions of the resistor (18) and a first integrated circuit feature (34), and a second parasitic capacitance (28) exists between second portions of the resistor and a second integrated circuit feature (32). The resistor (18) may have, for example, a zigzag or serpentine configuration, with portions of each leg of the zigzag configuration over-lying the first and second integrated circuit features (34,32). The first and second integrated circuit features (34,32) are configured to produce substantially canceling charges on the first and second parasitic capacitances (26,28). The resistor may be defined by a doped semiconductor material, such as a polysilicon layer. The resistor may be used in many applications, such as a feedback resistor of an optoelectronic current-to-voltage converter (12).

Abstract: A monolithic light-to-digital signal converter (1.10) includes a photodiode array (1.24) having a plurality of sections with each section producing a current signal in response to incident light, a current-to-digital signal converter circuit (1.28) for converting selected ones of the current signals to a digital signal, and a control circuit (1.26) for scaling the digital signal in response to user supplied programming signals. The control circuit (1.26) also responds to user supplied programming signals to supply control signals to current-to-digital signal converter circuit (1.28). Current-to-digital signal converter circuit (1.28) is responsive to the control signals for combining selected ones of the current signals into a composite current signal and converting the composite current signal to a digital signal.

Abstract: photosensor device (41) having tapered photodiodes (53, 55) that are interdigitated and which is compatible with typical ASIC, CMOS and BiCMOS processes. A left side photodiode array of tapered regions (53) of a first conductivity type is disposed into an epitaxial layer of a second conductivity type. This array of photodiodes is coupled together and further coupled to a first output terminal (43). A fight side photodiode array of tapered regions (55) of said first conductivity type is disposed into the epitaxial layer of the second conductivity type, spaced apart from the left side photodiode by a minimum distance. A second output terminal is coupled to the array of fight side photodiodes (51). An incident light spot (39) is focused onto the sensor. The amount of current generated at the first and second output terminals (43, 51) will be proportional to the area of the left photodiode array and the area of the fight photodiode array which is receiving light.

Abstract: A photosensor device (41) having tapered photodiodes (53, 55) that are interdigitated and which is compatible with typical ASIC, CMOS and BiCMOS processes. A left side photodiode array of tapered regions (53) of a first conductivity type is disposed into an epitaxil layer of a second conductivity type. This array of photodiodes is coupled together and further coupled to a first output terminal (43). A right side photodiode array of tapered regions (55) of said first conductivity type is disposed into the epitaxial layer of the second conductivity type, spaced apart from the left side photodiode by a minimum distance. A second output terminal is coupled to the array of right side photodiodes (51). An incident light spot (39) is focused onto the sensor. The amount of current generated at the first and second output terminals (43, 51) will be proportional to the area of the left photodiode array and the area of the right photodiode array which is receiving light.

Abstract: A buried P-N junction photodiode is obtained in LinBiCMOS process with junctions formed between N+DUF diffused region and both first P-EPI layer and second P-EPI layer. Contact to N+DUF diffused region is made by a small area deep N+collector diffusion or N well diffusion. This novel buried-junction photodiode can be used for several types of unique photodetector structures including: single photodiode with low surface leakage current, multi-junction photodiodes for incident light spectral distribution information and higher efficiency visible response photodetectors. The disclosed structures are compatible with bipolar and CMOS processes for providing on-chip integration of optical photodetectors with Linear ASIC standard cells and other circuit functions.

Abstract: A simple low-cost fiber optic connector having a body member into which a ferrule is inserted and held in place by an expandable retainer which allows the ferrule to snap out of the assembly upon the application of a substantial pulling force, and thereby avoid damage to the fiber or to the connector. A preferred embodiment includes two aligned ferrules inserted into opposite sides of the body such that their tips meet at the center to interconnect the ends of two optical fibers. A multiple-ferrule embodiment is also contemplated.