Abstract: A conductive bridge memory system and method of manufacture thereof including: providing a dielectric layer having a hole on a bottom electrode, the hole over the bottom electrode; forming an ionic source layer in the hole and over the bottom electrode including: depositing a reactivation layer over the bottom electrode, depositing a first ion source layer on the reactivation layer, depositing another of the reactivation layer on the first ion source layer, depositing a second ion source layer on the another of the reactivation layer; and forming an upper electrode on the ionic source layer.

Abstract: A conductive bridge memory system and method of manufacture thereof including: providing a dielectric layer having a hole on a bottom electrode, the hole over the bottom electrode; forming an ionic source layer in the hole and over the bottom electrode including: depositing a reactivation layer over the bottom electrode, depositing a first ion source layer on the reactivation layer, depositing another of the reactivation layer on the first ion source layer, depositing a second ion source layer on the another of the reactivation layer; and forming an upper electrode on the ionic source layer.

Abstract: A conductive bridge memory system and method of manufacture thereof including: providing a dielectric layer having a hole on a bottom electrode, the hole over the bottom electrode; forming an ionic source layer in the hole and over the bottom electrode including: depositing a reactivation layer over the bottom electrode, depositing a first ion source layer on the reactivation layer, depositing another of the reactivation layer on the first ion source layer, depositing a second ion source layer on the another of the reactivation layer; and forming an upper electrode on the ionic source layer.

Abstract: A conductive bridge memory system and method of manufacture thereof including: providing a dielectric layer having a hole on a bottom electrode, the hole over the bottom electrode; forming an ionic source layer in the hole and over the bottom electrode including: depositing a reactivation layer over the bottom electrode, depositing a first ion source layer on the reactivation layer, depositing another of the reactivation layer on the first ion source layer, depositing a second ion source layer on the another of the reactivation layer; and forming an upper electrode on the ionic source layer.

Abstract: Some embodiments include devices that contain bundles of CNTs. An undulating topography extends over the CNTs and within spaces between the CNTs. A global maximum lateral width is defined as the greatest lateral width of any of the spaces. A material is directly over the CNTs, with the material being a plurality of particles that have minimum cross-sectional equatorial widths exceeding the global maximum lateral width. Some embodiments include methods in which a plurality of crossed carbon nanotubes are formed over a semiconductor substrate. The CNTs form an undulating upper topography extending across the CNTs and within spaces between the CNTs. A global maximum lateral width is defined as the greatest lateral width of any of the spaces. A material is deposited over the CNTs, with the material being deposited as particles that have minimum cross-sectional equatorial widths exceeding the global maximum lateral width.

Abstract: The present invention provides atomic layer deposition systems and methods that include at least one compound of the formula (Formula I): Ta(NR1)(NR2R3)3, wherein each R1, R2, and R3 is independently hydrogen or an organic group, with the proviso that at least one of R1, R2, and R3 is a silicon-containing organic group. Such systems and methods can be useful for depositing tantalum silicon nitride layers on substrates.

Abstract: Some embodiments include devices that contain bundles of CNTs. An undulating topography extends over the CNTs and within spaces between the CNTs. A global maximum lateral width is defined as the greatest lateral width of any of the spaces. A material is directly over the CNTs, with the material being a plurality of particles that have minimum cross-sectional equatorial widths exceeding the global maximum lateral width. Some embodiments include methods in which a plurality of crossed carbon nanotubes are formed over a semiconductor substrate. The CNTs form an undulating upper topography extending across the CNTs and within spaces between the CNTs. A global maximum lateral width is defined as the greatest lateral width of any of the spaces. A material is deposited over the CNTs, with the material being deposited as particles that have minimum cross-sectional equatorial widths exceeding the global maximum lateral width.

Abstract: The present invention provides atomic layer deposition systems and methods that include at least one compound of the formula (Formula I): Ta(NR1)(NR2R3)3, wherein each R1, R2, and R3 is independently hydrogen or an organic group, with the proviso that at least one of R1, R2, and R3 is a silicon-containing organic group. Such systems and methods can be useful for depositing tantalum silicon nitride layers on substrates.

Abstract: The present invention provides atomic layer deposition systems and methods that include at least one compound of the formula (Formula I): Ta(NR1)(NR2R3)3, wherein each R1, R2, and R3 is independently hydrogen or an organic group, with the proviso that at least one of R1, R2, and R3 is a silicon-containing organic group. Such systems and methods can be useful for depositing tantalum silicon nitride layers on substrates.

Abstract: The present invention provides atomic layer deposition systems and methods that include at least one compound of the formula (Formula I): Ta(NR1)(NR2R3)3, wherein each R1, R2, and R3 is independently hydrogen or an organic group, with the proviso that at least one of R1, R2, and R3 is a silicon-containing organic group. Such systems and methods can be useful for depositing tantalum silicon nitride layers on substrates.

Abstract: A conductive structure, including an adhesion layer and a conductor in contact with the adhesion layer and having a thickness of less than six hundred Angstroms. The present invention may be used to form a capacitor, including an adhesion layer, a first conductor in contact with the adhesion layer and having a thickness of less than six hundred Angstroms, a second conductor, and a dielectric between the first and second conductors. The present invention is also directed towards structures wherein iridium or rhodium may be used in place of the combination of the adhesion layer and conductor.

Abstract: An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to the substrate within the atomic layer deposition chamber effective to form a first monolayer on the substrate. The first precursor gas flowing comprises a plurality of first precursor gas pulses. The plurality of first precursor gas pulses comprises at least one total period of time between two immediately adjacent first precursor gas pulses when no gas is fed to the chamber. After forming the first monolayer on the substrate, a second precursor gas different in composition from the first is flowed to the substrate within the deposition chamber effective to form a second monolayer on the first monolayer. Other aspects and implementations are contemplated.

Abstract: The use of atomic layer deposition (ALD) to form a conductive titanium nitride layer produces a reliable structure for use in a variety of electronic devices. The structure is formed by depositing titanium nitride by atomic layer deposition onto a substrate surface using a titanium-containing precursor chemical such as TDEAT, followed by a mixture of ammonia and carbon monoxide or carbon monoxide alone, and repeating to form a sequentially deposited TiN structure. Such a TiN layer may be used as a diffusion barrier underneath another conductor such as aluminum or copper, or as an electro-migration preventing layer on top of an aluminum conductor. ALD deposited TiN layers have low resistivity, smooth topology, high deposition rates, and excellent step coverage and electrical continuity.

Abstract: A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula LyRhYz is provided. Also provided is a chemical vapor co-deposited platinum-rhodium alloy barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The alloy barriers protect surrounding materials from oxidation during oxidative recrystallization steps and protect cell dielectrics from loss of oxygen during high temperature processing steps. Also provided are methods for CVD co-deposition of platinum-rhodium alloy diffusion barriers.

Abstract: A dielectric material forming method includes forming a first monolayer and forming a second monolayer on the first monolayer, one of the first and second monolayers comprising tantalum and oxygen and the other of the first and second monolayers comprising oxygen and another element different from tantalum. A dielectric layer can be formed containing the first and second monolayers. The dielectric layer can exhibit a dielectric constant greater than the first monolayer. The another element can include a Group IB to VIIIB element, such as titanium and/or zirconium. The forming of the first and second monolayer can include atomic layer depositing. A dielectric material can include first and second chemisorbed materials, the second material containing oxygen and a Group IB to VIIIB element and the dielectric material exhibiting a dielectric constant greater than the first chemisorbed material. The dielectric material can further exhibit less current leakage than the first material.

Abstract: Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge storage units in electronic structures for use in a wide range of electronic devices and systems. The isolated conductive nanoparticles may be used as a floating gate in a flash memory. In an embodiment, conductive nanoparticles are deposited on a dielectric layer by a plasma-assisted deposition process such that each conductive nanoparticle is isolated from the other conductive nanoparticles to configure the conductive nanoparticles as charge storage elements.

Abstract: A seed film and methods incorporating the seed film in semiconductor applications is provided. The seed film includes one or more noble metal layers, where each layer of the one or more noble metal layers is no greater than a monolayer. The seed film also includes either one or more conductive metal oxide layers or one or more silicon oxide layers, where either layer is no greater than a monolayer. The seed film can be used in plating, including electroplating, conductive layers, over at least a portion of the seed film. Conductive layers formed with the seed film can be used in fabricating an integrated circuit, including fabricating capacitor structures in the integrated circuit.

Abstract: The present invention provides techniques to fabricate high dielectric MIM storage cell capacitors. In one embodiment, this is accomplished by forming a silicon contact is then formed to electrically connect the formed bottom electrode layer in the container with the at least one associated transistor device. A titanium nitride barrier layer is then formed over the silicon contact. An oxygen barrier layer including platinum stuffed with silicon oxide is then formed over the titanium nitride layer and below the bottom electrode layer. A bottom electrode layer is then formed using platinum over interior surfaces of a container formed relative to at lest one associated transistor device on a silicon substrate. Further, a high dielectric insulator layer is formed over the bottom electrode layer. A top electrode layer is then formed over the high dielectric insulator layer.

Abstract: A seed film and methods incorporating the seed film in semiconductor applications is provided. The seed film includes one or more noble metal layers, where each layer of the one or more noble metal layers is no greater than a monolayer. The seed film also includes either one or more conductive metal oxide layers or one or more silicon oxide layers, where either layer is no greater than a monolayer. The seed film can be used in plating, including electroplating, conductive layers, over at least a portion of the seed film. Conductive layers formed with the seed film can be used in fabricating an integrated circuit, including fabricating capacitor structures in the integrated circuit.

Abstract: The present invention provides atomic layer deposition systems and methods that include at least one compound of the formula (Formula I): Ta(NR1)(NR2R3)3, wherein each R1, R2, and R3 is independently hydrogen or an organic group, with the proviso that at least one of R1, R2, and R3 is a silicon-containing organic group. Such systems and methods can be useful for depositing tantalum silicon nitride layers on substrates.