Abstract: A circuit for recording a magnitude of an ESD event during semiconductor assembly includes a voltage divider connected between an input and a ground. The circuit also includes a measurement block having a recorder device. Each measurement block receives current from a segment of the voltage divider. The magnitude of the ESD event is determined based upon a read-out of the measurement devices after the ESD event. The recorder device may be a capacitor that would be damaged during the ESD event. During the ESD event the capacitor may be damaged. Reading out the recorder device determines if the magnitude of the ESD event exceeded a threshold magnitude that damages the capacitor.

Abstract: According to an exemplary embodiment, an integrated circuit includes a first circuit block having a first power bus. The integrated circuit further includes a second circuit block having a second power bus, where the first power bus is isolated from the second power bus. The integrated circuit further includes a first dedicated ESD bus, where the first dedicated ESD bus provides a discharge path from the first power bus to the second power bus and from the second power bus to the first power bus. The first power bus can be coupled to the first dedicated ESD bus by a first pair to bi-directional diodes, and the second power bus can be coupled to the first dedicated ESD bus by a second pair of bi-directional diodes.

Abstract: An amplifier (e.g., an LNA) with improved ESD protection circuitry is described. In one exemplary design, the amplifier includes a transistor, an inductor, and a clamp circuit. The transistor has a gate coupled to a pad and provides signal amplification for the amplifier. The inductor is coupled to a source of the transistor and provides source degeneration for the transistor. The clamp circuit is coupled between the gate and source of the transistor and provides ESD protection for the transistor. The clamp circuit may include at least one diode coupled between the gate and source of the transistor. The clamp circuit conducts current through the inductor to generate a voltage drop across the inductor when a large voltage pulse is applied to the pad. The gate-to-source voltage (Vgs) of the transistor is reduced by the voltage drop across the inductor, which may improve the reliability of the transistor.

Abstract: According to an exemplary embodiment, a semiconductor structure includes an NFET situated over a substrate. The semiconductor structure further includes a P+ substrate tie ring surrounded the NFET. The P+ substrate tie ring includes a salicide layer situated on a P+ diffusion region. The semiconductor structure further includes an N well ring situated between the NFET and the P+ substrate tie ring, where the N well ring increases snap-back conduction uniformity in the NFET. The semiconductor structure further includes an N+ active ring situated between the NFET and the P+ substrate tie ring, where the N+ active ring surrounds the NFET and connects the P+ substrate tie ring to the N well ring. The N+ active ring includes a salicide layer situated on an N+ diffusion region, where the salicide layer of the N+ active ring connects the N well ring to the P+ substrate tie ring.

Abstract: An ESD protection circuit includes a field effect transistor device configured such that current flowing through a hot spot filament formed in a gate region must flow in a non-linear path from a drain contact to a source contact. Source diffusion areas are segmented and staggered relative to drain diffusion areas in order to provide the non-linear current path.

Abstract: According to one exemplary embodiment, an ESD bus clamp in an integrated circuit comprises an inverter having an input and an output. The ESD bus clamp further comprises a bipolar transistor having a base, an emitter, and a collector, where the base is connected to the output of the inverter, the emitter is connected to a ground of the integrated circuit, and the collector is connected to a power bus of the integrated circuit. The bipolar transistor, for example, may be an NPN bipolar transistor and may begin shunting current to the ground when an ESD discharge causes a voltage level on the power bus to increase by approximately 1.0 volt. According to this exemplary embodiment, the ESD bus clamp further comprises a resistor coupling the input of the inverter to the power bus. The ESD bus clamp further comprises a capacitor coupling the input of the inverter to ground.

Abstract: An LED lamp package for packaging an LED driver with an LED is provided. In one embodiment, the LED lamp package includes an LED driver chip and an LED chip, both of which are mounted on the ground lead of the LED lamp package and both of which are enclosed by the light transparent encapsulant of the LED lamp package. In another embodiment, the LED chip is mounted on top of the LED driver chip in the LED lamp package. In this embodiment, the LED driver chip includes an attachment pad, on which the bottom surface of the LED chip is mounted.

Abstract: An electrostatic discharge (ESD) protection circuit comprises a P-channel field effect transistor (PFET), a buffer and a damping network to provide improved protection for an integrated circuit against high-voltage ESD pulses. The ESD protection circuit is capable of being fabricated with a reduced surface area layout to be fully synthesisable with the integrated circuit which it is designed to protect.

Abstract: A diode for improved electrostatic discharge (ESD) protection against current failure includes a plurality of elongate anode and cathode conductor stripes each having first and second end portions of different widths to reduce current densities at feeder bus tie points, thereby reducing the possibility of current failure.

Abstract: An LED lamp package for packaging an LED driver with an LED is provided. In one embodiment, the LED lamp package includes an LED driver chip and an LED chip, both of which are mounted on the ground lead of the LED lamp package and both of which are enclosed by the light transparent encapsulant of the LED lamp package. In another embodiment, the LED chip is mounted on top of the LED driver chip in the LED lamp package. In this embodiment, the LED driver chip includes an attachment pad, on which the bottom surface of the LED chip is mounted.

Abstract: The switching properties of the disclosed device, low off current and high on current, also allows the device to be employed to replace EEPROM, fuses, anti-fuses or other electrically-alterable non volatile switching devices in programmable logic devices. The disclosed device can be fabricated with low cost methods. The manufacturing methods are compatible with current tools and procedures which allows the device to be added to CMOS circuits to replace masked ROM with more flexible flash memory at a modest increase in cost. The cell operational method and manufacturing methods allows the size of the memory element to be scaled smaller to maintain a low cost and high performance as the minimum feature size of microelectronic circuits is reduced in the future. The disclosed cell approach also offers simpler programming methods to simplify memory array design, supports higher cell currents for high speed applications, and uses lower cost manufacturing methods than an "ETOX" cell approach.

Abstract: Micro-mechanical flappers for use as an electronic display technology and methods related to the fabrication thereof are disclosed. These methods are consistent with standard silicon based semiconductor processing used to make integrated circuits. One embodiment shows how cross-talk or flapper-to-flapper interference is minimized using a Digital Signal Processor (DSP) to compensate for this undesirable effect. Also disclosed is the construction of a micro-mechanical flapper that uses a combination of two springs, viz. a leaf spring and a torsion spring, to reduce maximum bending stress and to lower operating voltage. Also, the spring construction is made such that axial stability is improved over a single leaf spring approach and a light shield is integrated onto the flapper assembly so that the overhead stationary electrode is simply a supporting glass plate with a transparent conducting layer over its surface.

Abstract: A single clamp circuit for integrated circuits with multiple V.sub.dd power pins by coupling the various V.sub.dd busses to an ESD clamped V.sub.dd bus or pseudo- V.sub.dd bus via diodes. The diodes will provide coupling from any V.sub.dd bus to the clamp circuit during a positive ESD transient. A diode for each V.sub.dd bus and a single clamp circuit can be much more area efficient than a single clamp circuit for each V.sub.dd bus. During normal operation, the diodes will become weakly forward biased due to the leakage current of the clamp circuit. Small signal noise will tend not to be coupled from one bus to the other because of the high impedance of the diodes. For a large positive noise transient on one bus, the other bus diode will reverse bias, thus decoupling the signal from the other busses. A large negative noise transient on one bus will cause its diode to reverse bias thus decoupling it from the other busses.

Abstract: A micro-mechanical shutter array using micro-mechanical technology and silicon-on-transparent-substrate technology. The micro-mechanical shutter array is operated by using electro-static forces. Two basic types of shutter movements are described, viz. an electric force/electric counter-force and an electric force/mechanical (spring) counter-force.

Abstract: A monolithic opto-coupler employing silicon-insulator technology in which at least two p-type silicon islands disposed on said insulating layer and a light emitting diode having enhanced light emitting efficiency is formed on one of said islands. The enhanced light emitting diode is either of the type having the surface of said p-type silicon island being electrochemically etched to provide a porous silicon layer, having carbon implanted in damaged silicon, or having an amorphous silicon-carbide layer. A silicon diode detector is formed on the other island(s) and a reflective layer is disposed over the light-emitting diode and the detectors for coupling light generated in the light emitting diode to the silicon diode detector.

Abstract: An ESD protection circuit for the pads of an integrated circuit (IC) using silicide-clad diffusions is disclosed. The circuit uses a robust N+ diode with N-well block, an output NFET and a large transient clamp, each with a distributed, integrated N-well drain resistor to prevent the IC from avalanching and leakage during the Human Body Model and Charged Device Model tests for ESD.

Abstract: Isolation circuits for optically passing signals between a plurality of electrical circuits without any electrically conductive path therebetween. The circuits utilize monolithic, silicon-on-insulator and integrated circuit techniques.

Abstract: A high voltage level input protection, high capacitance output IC clock receiver uses a ratioed CMOS buffer for the output drive and the receiver includes a low resistance input circuit having a pair of series connected large area input diodes physically located beneath the pad in an input network including a pair of gate controlled diodes in parallel therewith and a low value input resistor connected between the pad diodes and the gate controlled diodes. An N+ resistor receives the CMOS level output on a large metal bus from which metal interconnects fan-out to apply the clock signal to a plurality of loads in synchronism with diminished delay and increased reliability. Thus, reducing the resistance required in the input protection circuit improves the synchronism.

Abstract: The invention applies a weak forward bias to the body of the NFET transistor of a PFET-NFET TTL inverter buffer circuit to lower the NFET threshold voltage by about 0.45 volts, as a result of 1.5.mu. amps of body-source current providing a body to source voltage of about 0.5 volts to achieve a near ideal switch point of 1.45 volts under nominal conditions. Also a modified inverter circuit with biasing source, two diodes for trip voltage of 1.4 volts and a comparator constitute a central bias generator for supplying proper bias to the body of the NFETs of a plurality of TTL input buffers.

Abstract: An improved driver circuit for an integrated gate circuit using Gallium Arsenide direct coupled FET logic. The push-pull driver circuit generally comprises an enhancement mode voltage follower transistor for driving a load during a first logic transition, and an enhancement mode pull-down transistor for driving this load during a second logic transition. Since only one of these transistors are conductive during these logic transitions (i.e., LO to HI, and HI to LO), little or no static current flows through these transistor means during steady state conditions. Thus, particularly for large capacitive loads, the driver circuit will be considerably faster than conventional DCFL technology, while not causing a significant increase in the power consumed by the push-pull driver circuit.