Abstract: Apparatus and methods for translation of data formats between multiple interface types. Translation logic is interposed between a producer circuit and a consumer circuit to translate data formats of data signals generated by the producer for application to the consumer. The translation logic may include multiple translators to provide translations between any of multiple producer data formats and any of multiple consumer data formats. One or more producer circuits may thus be selectively coupled with one or more consumer circuits through the translation logic circuit.

Abstract: Methods and systems for processing a second request before processing of a first request has completed. The first request is associated with a first flow control credit type, and the second request is associated with a second flow control credit type. After a period of time, the second request is selected for processing based on the first flow control credit type and the second flow control credit type.

Abstract: Apparatus methods for capturing flow control errors in FIFO exchanges between producing and consuming circuits operating in different clock domains. Tag information at the start of an exchange is transferred to a synchronizing component before data of a transfer transaction is entered in the FIFO. The tag information is also associated with each unit of data transferred to the FIFO by the producing circuit. The synchronizing component verifies the each unit of data retrieved by the consuming circuit has the expected tag information associated therewith and signals an error is the tag information does not match. Thus an error by the producing circuit in entering too much or too little data for a transfer is detected before erroneous data is retrieved and processed by the consuming circuit.

Abstract: A packet alignment system for pre-processing/aligning incoming packets may comprise one or more registers for receiving control signals and data signals. An aligner may cyclically shift said data signals to form a plurality of shifted data words. A plurality of pipe registers may collect and generate an adjusted control signal for each one of the plurality of shifted data words. A filtering logic may identify one of the plurality of shifted data words as a desired aligned data word. The filter logic may also be configured for registering header data, payload data and ECRC data contained in the desired aligned data word in a header register, a payload register and an ECRC register, respectively. An output interface may generate an outgoing signal and provide data from at least one of the header register, the payload register and the ECRC register.

Abstract: Methods and systems for processing a second request before processing of a first request has completed. The first request is associated with a first flow control credit type, and the second request is associated with a second flow control credit type. After a period of time, the second request is selected for processing based on the first flow control credit type and the second flow control credit type.

Abstract: Apparatus and methods for translation of data formats between multiple interface types. Translation logic is interposed between a producer circuit and a consumer circuit to translate data formats of data signals generated by the producer for application to the consumer. The translation logic may include multiple translators to provide translations between any of multiple producer data formats and any of multiple consumer data formats. One or more producer circuits may thus be selectively coupled with one or more consumer circuits through the translation logic circuit.

Abstract: Apparatus methods for capturing flow control errors in FIFO exchanges between producing and consuming circuits operating in different clock domains. Tag information at the start of an exchange is transferred to a synchronizing component before data of a transfer transaction is entered in the FIFO. The tag information is also associated with each unit of data transferred to the FIFO by the producing circuit. The synchronizing component verifies the each unit of data retrieved by the consuming circuit has the expected tag information associated therewith and signals an error is the tag information does not match. Thus an error by the producing circuit in entering too much or too little data for a transfer is detected before erroneous data is retrieved and processed by the consuming circuit.

Abstract: A method for determining when all data has been sent for a given PCI Express bus command issued by a backend entity of a PCI Express bus device, by setting a PCI Express bus packet header tag field of a PCI Express bus packet to indicate a backend entity that originated the PCI Express bus command and whether the PCI Express bus packet is a last packet of the PCI Express bus command, and then inspecting the PCI Express bus packet header tag field of the PCI Express bus packet to determine whether the PCI Express bus packet is the last packet of the PCI Express bus command.

Abstract: Disclosed is a system that generates a write count value for indicating whether data can be read from a FIFO and a system that generates a read count value for indicating whether data can be written to a FIFO. Each of these systems operates in two separate clock domains. In the system that generates a write count value, write strobes are stored in parallel in a register in a first clock domain. The plurality of synchronizers trigger on a rising edge of the write strobe that is stored in the parallel register and generate an increment pulse in a second clock domain. An up/down counter reads the increment pulse in parallel and increments the up/down counter in parallel. A decrement signal from a read strobe decrements the up/down counter. The output of the counter is fed to a register that provides a write counter value to handshake logic that indicates whether data can be read from a FIFO without underflowing the FIFO.

Abstract: A packet alignment system for pre-processing/aligning incoming packets may comprise one or more registers for receiving control signals and data signals. An aligner may cyclically shift said data signals to form a plurality of shifted data words. A plurality of pipe registers may collect and generate an adjusted control signal for each one of the plurality of shifted data words. A filtering logic may identify one of the plurality of shifted data words as a desired aligned data word. The filter logic may also be configured for registering header data, payload data and ECRC data contained in the desired aligned data word in a header register, a payload register and an ECRC register, respectively. An output interface may generate an outgoing signal and provide data from at least one of the header register, the payload register and the ECRC register.

Abstract: Disclosed is a system that generates a write count value for indicating whether data can be read from a FIFO and a system that generates a read count value for indicating whether data can be written to a FIFO. Each of these systems operates in two separate clock domains. In the system that generates a write count value, write strobes are stored in parallel in a register in a first clock domain. The plurality of synchronizers trigger on a rising edge of the write strobe that is stored in the parallel register and generate an increment pulse in a second clock domain. An up/down counter reads the increment pulse in parallel and increments the up/down counter in parallel. A decrement signal from a read strobe decrements the up/down counter. The output of the counter is fed to a register that provides a write counter value to handshake logic that indicates whether data can be read from a FIFO without underflowing the FIFO.

Abstract: An adapter card for testing the functionality of a particular interface configuration may include an interface core. The interface core may comprise an electric circuit including electronic components and control logic for interfacing with an information handling system device. The adapter card may include a front end data channel coupled with the interface core for transmitting data between the electronic components and the information handling system device. The adapter card may include firmware for setting an indicator and causing the control logic to report a memory requirement to the information handling system device larger than a programmed memory space expected by the control logic.

Abstract: A method and apparatus for traversing a queue of commands containing a mixture of read and write commands places a Next Valid Write Address pointer in each queue entry. In this manner, time savings are achieved by allowing preprocessing of the next write command to be executed. The method may be practiced by setting a next valid address pointer in all queue entries. Queue traversal may be forward, backward, or bi-directional.

Abstract: A loop of delayed read commands is established from a larger set of queued commands. Upon recognizing a delay in completing a first read command which is followed by a second read command, the loop is established by setting loop start pointer to identify the first delayed read command and setting a loop end pointer to identify the second read command. Upon recognizing a delay in completing the second read command which is followed by a third read command, the loop end pointer is advanced to identify the third read command. All of the read commands in the loop at and between the loop start pointer and the loop end pointer are completed before attempting to complete other commands in the queue not within the loop.

Abstract: A method and apparatus for traversing a queue of commands containing a mixture of read and write commands places a Next Valid Write Address pointer in each queue entry. In this manner, time savings are achieved by allowing preprocessing of the next write command to be executed. The method may be practiced by setting a next valid address pointer in all queue entries. Queue traversal may be forward, backward, or bi-directional.