Abstract: An apparatus is described comprising an ingress port and a plurality of switch planes where each of the switch planes has a dedicated scheduler and each of the switch planes are communicatively coupled to the ingress port. The switch planes may further have at least one input control port and at least one output control port where each of the input control ports are coupled to each of the output control ports in a crossbar arrangement. The communicative coupling may further comprise one of the input control ports coupled to the ingress port. Furthermore, the ingress port may have at least one unicast queue which is dedicated to a specific egress port. The ingress port may also have a multicast queue.

Abstract: An apparatus and method of compensating for differences in circuit routing path lengths is described. In one embodiment, a latch is inserted between reset signal generating logic and a pair of flip-flops. When a reset signal is generated, the reset signal is held inside the latch until both flip-flops are reset. A latch reset signal may be generated by the flip-flops to clear the latch. The circuit may be configured to ensure that both flip-flops are reset before the reset signal is disabled.

Abstract: A method and apparatus for rate-based cell traffic arbitration in a switch are provided, wherein arbitration is provided between eight traffic sources in the form of eight cell bus service modules on the same cell bus. A cell bus controller (CBC) is programmed with an 8-bit Relative Service Delay (RSD) value for each of the eight service modules. The value for each RSD is calculated based on the bandwidths allotted for each service module. This RSD value determines the portion of the total bandwidth of the switch platform reserved for the respective service module. Furthermore, each service module uses an 8-bit Service Delay Accumulator (SDA) register. The SDA register of each service module is configured using an SDA value, wherein the SDA register keeps track of when each of the service modules should receive service.

Abstract: A method and apparatus for routing cells having different formats among service modules of a switch platform are provided. The cells are routed among service modules of a switch by a cell bus controller (CBC) using a first memory to convert an address having a first format into an address having a second format. The address having the first format is received in a header of a cell, and the address format comprises a 17-bit cell bus logical connection number of a destination port. The address having the second format is a 16-bit UDF used by a switch of the switch platform. The address having the first format is used to form a third address that is used to access the first memory. The data located at the third address of the first memory is a 16-bit UDF used to address the switch. A second memory is used to convert an address having the second format into an address having the first format. The address having the second format is used as a fourth address to access the second memory.

Abstract: A method and apparatus for providing cell bus management in a switch platform are provided. Each unidirectional FIFO buffer of a cell bus controller outputs a write port cell count from a write port. A cell count value is programmed at which the write port cell count is outputted. When the write port cell count indicates that the FIFO buffer can not accept additional data or cells, a master bidirectional FIFO unit ceases reading cells to a unidirectional FIFO buffer of the slave bidirectional FIFO unit in response to the write port cell count. Furthermore, the master bidirectional FIFO unit disables a corresponding switch from routing cells to the slave bidirectional FIFO unit in response to the write port cell count; the switch routes the cells to another of the slave bidirectional FIFO units.

Abstract: A method and apparatus for providing asynchronous memory functions for bi-directional cell traffic in a switch platform are provided, wherein a parameterized bi-directional FIFO unit controls cell traffic in a switch platform using a first and a second unidirectional FIFO buffer. The first and second unidirectional FIFO buffers each comprises asynchronous read and write ports. A cell size and a word size of the first and second unidirectional FIFO buffers are programmable. The bi-directional FIFO unit is coupled to write at least one cell from and read at least one cell to at lest one asynchronous transfer mode (ATM) interface, at least one frame relay interface, at least one voice interface, and at least one data interface. As such, the first unidirectional FIFO buffer is coupled to write at least one cell from, and the second unidirectional FIFO buffer is coupled to read at least one cell to an ATM interface, a frame relay interface, a voice interface, and a data interface.

Abstract: Methods, systems and computer software products are provided for determining genotype of a sample using a plurality of probes. In one preferred embodiment, a tentative genotype call is made based upon the relative allele signals. Pattern recognition is then used to validate the tentative call.

Abstract: A method and apparatus for transporting digital images is provided. In one embodiment, a personal electronic handheld digital camera executes an application program that enables a user of the camera to send one or more digital images, formed by and stored in the camera, from the camera to a destination. One or more addresses describing one or more destinations are selected or identified. One or more stored digital images are selected and associated with the one or more addresses. Optionally, a voice message is recorded and associated with the one or more addresses. The camera is coupled to a data communication network, and a transport operation is initiated. Under control of the application, the camera sends the selected images to the designated destinations over the data communication network. When an address is a physical address, for example, a postal mail address, the selected images are automatically routed to a central server.

Abstract: A selectable timing delay system which provides for delaying an input signal a specified length of time within a specified tolerance wherein the range and resolution of the selectable timing delay system are so specified that the selected delay within the selected tolerance is obtainable regardless of the relative speed of the integrated circuit chips used in forming the selectable timing delay system.

Abstract: An apparatus is provided for synchronously selecting different oscillators as the system clock source. The apparatus is comprised of two oscillator selectors. Each of the oscillator selectors has as its inputs the output of each of the oscillators and a three-bit command code which indicates which of the oscillators is to be selected by the oscillator selector and a single clock output. A different oscillator may be selected by each of the oscillator selectors at the same time. The output of the oscillator selectors are inputs to the clock controller. The clock controller also receives command signals for controlling the switching of the clock controller between the outputs of the two oscillator selectors. The output of the clock controller is the clock source for the system and a status signal indicating which oscillator selector is presently being used.