Patents by Inventor Eui-Cheol Lim
Eui-Cheol Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240045861Abstract: A system for classifying data may include a memory, and a processor configured to determine a scan target including a data group selected from among data groups stored in the memory, based on a result of a comparison between first similarities of data groups stored in the memory and an externally received query, and a minimum value of second similarities of pieces of data included in a data group having a maximum value of the first similarities and the query, and to output, as result data responding to the query, scan data selected depending on a reference number of pieces of scan data from among pieces of scan data in the data group included in the scan target.Type: ApplicationFiled: February 13, 2023Publication date: February 8, 2024Inventors: Joon Seop SIM, Eui Cheol LIM
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Publication number: 20230376767Abstract: A device for partitioning an input neural network includes an interposing circuit configured to determine a partitioning position to at which the input neural network is to be partitioned, to interpose a partitioning layer in the input neural network at the partitioning position; and to output and entire neural network that is obtained by interposing the partitioning layer in the input neural network, a training circuit configured to train the entire neural network; and a partitioning circuit configured to divide the entire neural network into a plurality of neural network partitions by partition the partitioning layer. The input neural network includes a plurality of layers.Type: ApplicationFiled: October 20, 2022Publication date: November 23, 2023Inventors: Yeseong Kim, Jongho Park, Hyukjun Kwon, Seowoo Kim, Minho Ha, Eui Cheol Lim
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Patent number: 11734168Abstract: A storage device can be designed to reduce latency in a read operation. Such a storage device can include: a memory device including a plurality of pages that include a first page and a second page different from the first page, each page including a plurality of memory cells that are configured to store data; and a memory controller in communication with the memory device and for sequentially storing result values of a function with respect to a plurality of input values in the plurality of memory cells, and controlling the memory device to store a result value in a last area of the first page and a start area of the second page.Type: GrantFiled: June 4, 2021Date of Patent: August 22, 2023Assignee: SK hynix Inc.Inventors: Seung Yong Lee, Eui Cheol Lim, Myoung Seo Kim
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Patent number: 11487473Abstract: A memory system is disclosed, which relates to technology for implementing data communication between memory devices. The memory system includes a plurality of memory devices and a memory controller. The memory devices allow a data packet composed of data and header information to be directly communicated between the memory devices. The memory controller transmits the data packet to a source memory device from among the plurality of memory devices, and receives the data packet from a last memory device from among the plurality of memory devices. Each of the memory devices hashes the header information such that the data is accessed, using a result of the hash, in address regions located at different positions.Type: GrantFiled: December 24, 2020Date of Patent: November 1, 2022Assignee: SK hynix Inc.Inventors: Chang Hyun Kim, Eui Cheol Lim, Young Jung Choi, Hyung Sik Won, Sun Woong Kim
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Publication number: 20220245066Abstract: A memory system includes a first memory device having a first memory that includes a plurality of access management regions and a first access latency, each of the access management regions including a plurality of pages, the first memory device configured to detect a hot access management region having an access count that reaches a preset value from the plurality of access management regions, and detect one or more hot pages included in the hot access management region; and a second memory device having a second access latency that is different from the first access latency of the first memory device. Data stored in the one or more hot pages is migrated to the second memory device.Type: ApplicationFiled: April 22, 2022Publication date: August 4, 2022Inventors: Mi Seon HAN, Myoung Seo KIM, Yun Jeong MUN, Eui Cheol LIM
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Publication number: 20220188243Abstract: A memory module may include J memory chips configured to input/output data in response to each of a plurality of translated address signals; and an address remapping circuit configured to generate a plurality of preliminary translated address signals by adding first correction values to a target address signal provided from an exterior of the memory module, and to generate the plurality of translated address signals by shifting all bits of each of the plurality of preliminary translated address signals so that K bits included in a bit string of each of the plurality of preliminary translated address signals are moved to other positions of each bit string.Type: ApplicationFiled: December 6, 2021Publication date: June 16, 2022Applicant: SK hynix Inc.Inventors: Sung Woo HYUN, Hyeong Tak JI, Myoung Seo KIM, Jae Hoon KIM, Eui Cheol LIM
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Publication number: 20220164280Abstract: A storage device can be designed to reduce latency in a read operation. Such a storage device can include: a memory device including a plurality of pages that include a first page and a second page different from the first page, each page including a plurality of memory cells that are configured to store data; and a memory controller in communication with the memory device and for sequentially storing result values of a function with respect to a plurality of input values in the plurality of memory cells, and controlling the memory device to store a result value in a last area of the first page and a start area of the second page.Type: ApplicationFiled: June 4, 2021Publication date: May 26, 2022Inventors: Seung Yong LEE, Eui Cheol LIM, Myoung Seo KIM
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Publication number: 20220147274Abstract: A storage device includes: a memory device including memory cells for storing data, the memory cells grouped into a plurality of memory banks; and a memory controller coupled in communication with the memory device and configured to provide commands to the memory device and access one or more memory banks based on address information associated with the commands. The memory controller may count a number of access times that the memory controller has accessed to first memory bank by increasing the number of access times to the first memory bank based on a time interval between first active command and second active command for the first memory bank, and transmit, to the memory device, a control signal to perform a refresh operation on the first memory bank when the number of access times counted exceeds a predetermined number.Type: ApplicationFiled: May 13, 2021Publication date: May 12, 2022Inventors: Jae Hoon KIM, Eui Cheol LIM
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Patent number: 11288012Abstract: A memory system is disclosed, which relates to technology for implementing data communication between memory devices. The memory system includes a plurality of memory devices and a memory controller. The memory devices allow a data packet composed of data and header information to be directly communicated between the memory devices. The memory controller transmits the data packet to a source memory device from among the plurality of memory devices, and receives the data packet from a last memory device from among the plurality of memory devices. Each of the memory devices hashes the header information such that the data is accessed, using a result of the hash, in address regions located at different positions.Type: GrantFiled: April 24, 2020Date of Patent: March 29, 2022Assignee: SK hynix Inc.Inventors: Chang Hyun Kim, Eui Cheol Lim, Young Jung Choi, Hyung Sik Won, Sun Woong Kim
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Publication number: 20220058157Abstract: A data processing system including a shared memory; a host processor configured to possess an ownership of the shared memory, and process a first task by accessing the shared memory; a processor configured to possess the ownership transferred from the host processor, and process a second task by accessing the shared memory; and a memory controller coupled among the host processor, the processor, and the shared memory, and configured to allow the host processor or the processor to access the shared memory according to the ownership.Type: ApplicationFiled: October 26, 2021Publication date: February 24, 2022Applicant: SK hynix Inc.Inventors: Ji Hoon NAM, Eui Cheol LIM
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Patent number: 11170862Abstract: A memory system includes a non-volatile memory device and a controller. The non-volatile memory device includes a plurality of memory regions, each memory region including a plurality of cells commonly coupled to a word line. The controller generates a plurality of candidate data sets based on source data, determines a number of vulnerable cells corresponding to each of the plurality of candidate data sets, and stores a candidate data set having a smallest number of vulnerable cells into a target memory region among the plurality of memory regions.Type: GrantFiled: August 20, 2020Date of Patent: November 9, 2021Assignee: SK hynix Inc.Inventors: Mi Seon Han, Myoung Seo Kim, Eui Cheol Lim
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Patent number: 11169953Abstract: A data processing system including a shared memory; a host processor configured to possess an ownership of the shared memory, and process a first task by accessing the shared memory; a processor configured to possess the ownership transferred from the host processor, and process a second task by accessing the shared memory; and a memory controller coupled among the host processor, the processor, and the shared memory, and configured to allow the host processor or the processor to access the shared memory according to the ownership.Type: GrantFiled: December 5, 2018Date of Patent: November 9, 2021Assignee: SK hynix inc.Inventors: Ji Hoon Nam, Eui Cheol Lim
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Publication number: 20210318819Abstract: A data processing system includes a plurality of processors, a memory, a non-volatile memory, and a memory controller. The operational memory includes a first memory region and a second memory region. The memory controller performs a first swap operation of releasing assignment of a memory area assigned to a first processor within the first memory region, the first swap operation performed by moving data from the memory area to the second memory region. The memory controller performs a second swap operation by moving the data from the second memory region to the non-volatile memory when a second swap condition is satisfied after completion of the first swap operation.Type: ApplicationFiled: September 1, 2020Publication date: October 14, 2021Inventors: Yun Jeong MUN, Eui Cheol LIM, Mi Seon HAN, Myoung Seo KIM
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Publication number: 20210295933Abstract: A memory system includes a non-volatile memory device and a controller. The non-volatile memory device includes a plurality of memory regions, each memory region including a plurality of cells commonly coupled to a word line. The controller generates a plurality of candidate data sets based on source data, determines a number of vulnerable cells corresponding to each of the plurality of candidate data sets, and stores a candidate data set having a smallest number of vulnerable cells into a target memory region among the plurality of memory regions.Type: ApplicationFiled: August 20, 2020Publication date: September 23, 2021Inventors: Mi Seon HAN, Myoung Seo KIM, Eui Cheol LIM
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Publication number: 20210271600Abstract: A data storage device may include: a first memory configured to store a plurality of instructions and data required during an application operation; a cache configured to read, from the first memory, first data for operating the application and store the read first data therein; a processor configured to propagate a data read request to the first cache, a prefetcher, or both when a pointer chasing instruction is generated or a cache miss for the first cache occurs while the processor reads one or more instructions of the plurality of instructions and executes an application; and the prefetcher configured to read second data associated with the pointer chasing instruction or the cache miss from the first memory, and propagate the read second data to the cache.Type: ApplicationFiled: June 30, 2020Publication date: September 2, 2021Inventors: Jung Min CHOI, Byung Il KOH, Eui Cheol LIM
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Publication number: 20210132910Abstract: An arithmetic device includes a multiplying-accumulating (MAC) operator and an activation function (AF) circuit. The MAC operator performs a MAC arithmetic operation for weight data and vector data to generate an arithmetic result signal. The AF circuit stores a look-up table for an activation function, adjusts a number of logic level combinations of an input distribution signal that correspond to each logic level combination of the output distribution signal, among a plurality of logic level combinations of the output distribution signal, based on an input range of the activation function. The AF circuit selects and outputs the output distribution signal that corresponds to the input distribution signal based on the look-up table. The input range of the activation function is based on a relative number of errors that occur.Type: ApplicationFiled: January 11, 2021Publication date: May 6, 2021Applicant: SK hynix Inc.Inventors: Seung Yong LEE, Eui Cheol LIM, Choung Ki SONG, Myoung Seo KIM
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Publication number: 20210117131Abstract: A memory system is disclosed, which relates to technology for implementing data communication between memory devices. The memory system includes a plurality of memory devices and a memory controller. The memory devices allow a data packet composed of data and header information to be directly communicated between the memory devices. The memory controller transmits the data packet to a source memory device from among the plurality of memory devices, and receives the data packet from a last memory device from among the plurality of memory devices. Each of the memory devices hashes the header information such that the data is accessed, using a result of the hash, in address regions located at different positions.Type: ApplicationFiled: December 24, 2020Publication date: April 22, 2021Inventors: Chang Hyun KIM, Eui Cheol LIM, Young Jung CHOI, Hyung Sik WON, Sun Woong KIM
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Publication number: 20210064535Abstract: A memory system includes a first memory device having a first memory that includes a plurality of access management regions and a first access latency, each of the access management regions including a plurality of pages, the first memory device configured to detect a hot access management region having an access count that reaches a preset value from the plurality of access management regions, and detect one or more hot pages included in the hot access management region; and a second memory device having a second access latency that is different from the first access latency of the first memory device. Data stored in the one or more hot pages is migrated to the second memory device.Type: ApplicationFiled: April 3, 2020Publication date: March 4, 2021Inventors: Mi Seon HAN, Myoung Seo KIM, Yun Jeong MUN, Eui Cheol LIM
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Patent number: 10915470Abstract: A memory system is disclosed, which relates to technology for an accelerator of a high-capacity memory device. The memory system includes a plurality of memories configured to store data therein, and a pooled memory controller (PMC) configured to perform map computation by reading the data stored in the plurality of memories and storing resultant data produced by the map computation in the plurality of memories.Type: GrantFiled: March 28, 2019Date of Patent: February 9, 2021Assignee: SK hynix Inc.Inventors: Sun Woong Kim, Eui Cheol Lim
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Patent number: 10853278Abstract: A memory system is disclosed, which relates to technology for an accelerator of a high-capacity memory device. The memory system includes a plurality of memories configured to store data therein, and a pooled memory controller (PMC) configured to perform map computation by reading the data stored in the plurality of memories and storing resultant data produced by the map computation in the plurality of memories.Type: GrantFiled: March 28, 2019Date of Patent: December 1, 2020Assignee: SK hynix Inc.Inventors: Sun Woong Kim, Eui Cheol Lim