Abstract: A memory system is disclosed, which relates to technology for implementing data communication between memory devices. The memory system includes a plurality of memory devices and a memory controller. The memory devices allow a data packet composed of data and header information to be directly communicated between the memory devices. The memory controller transmits the data packet to a source memory device from among the plurality of memory devices, and receives the data packet from a last memory device from among the plurality of memory devices. Each of the memory devices hashes the header information such that the data is accessed, using a result of the hash, in address regions located at different positions.

Abstract: An accelerating apparatus for a neural network may include: an input processor configured to decide a computation mode according to precision of an input signal, and change or maintain the precision of the input signal according to the decided computation mode; and a computation circuit configured to receive the input signal from the input processor, perform select one or more operations among multiple operations including a multiplication based on the input signal, boundary migration to rearrange multiple signals divided from the input signal, and an addition of the input signal subjected to the boundary migration, according to the computation mode, and perform the selected one or more operations on the input signal.

Abstract: A memory system is disclosed, which relates to technology for an accelerator of a high-capacity memory device. The memory system includes a plurality of memories configured to store data therein, and a pooled memory controller (PMC) configured to perform map computation by reading the data stored in the plurality of memories and storing resultant data produced by the map computation in the plurality of memories.

Abstract: A data processing system including a shared memory; a host processor configured to possess an ownership of the shared memory, and process a first task by accessing the shared memory; a processor configured to possess the ownership transferred from the host processor, and process a second task by accessing the shared memory; and a memory controller coupled among the host processor, the processor, and the shared memory, and configured to allow the host processor or the processor to access the shared memory according to the ownership.

Abstract: A bus interface device for requesting and receiving data from a memory controller connected to a bus includes a request buffer and a request merger. The request buffer is configured to store a first data request signal for requesting first data and a second data request signal for requesting second data. The request merger is configured to determine whether to merge the first and second data request signals, and transmit a merged request signal for requesting the first data and the second data from the memory controller to the bus upon determining that the first and second data request signals are to be merged.

Abstract: A semiconductor device includes a first processing unit configured to perform a calculation by using data stored in a memory; and a memory path controller configured to communicate with the first processing unit and control the memory for the first processing unit to perform the calculation, wherein the memory path controller includes an address region control unit configured to divide an address space of the memory to include a secure address and a non-secure address and permit the first processing unit to access the secure address or the non-secure address, and a first content firewall unit connected with the address region control unit and configured to prevent the first processing unit from writing secure contents in the non-secure address.

Abstract: A bus interface device for requesting and receiving data from a memory controller connected to a bus includes a request buffer and a request merger. The request buffer is configured to store a first data request signal for requesting first data and a second data request signal for requesting second data. The request merger is configured to determine whether to merge the first and second data request signals, and transmit a merged request signal for requesting the first data and the second data from the memory controller to the bus upon determining that the first and second data request signals are to be merged.

Abstract: A semiconductor device includes a first processing unit configured to perform a calculation by using data stored in a memory; and a memory path controller configured to communicate with the first processing unit and control the memory for the first processing unit to perform the calculation, wherein the memory path controller includes an address region control unit configured to divide an address space of the memory to include a secure address and a non-secure address and permit the first processing unit to access the secure address or the non-secure address, and a first content firewall unit connected with the address region control unit and configured to prevent the first processing unit from writing secure contents in the non-secure address.

Abstract: A method of operating a semiconductor memory device includes receiving a timeout index signal corresponding to a master of the first master group based on a residual capacity of a data buffer of the first master, setting a first timeout value in response to the timeout index signal, and changing an execution order of commands stored in a queue of the semiconductor memory device based on a result of counting the first timeout value and counting a second timeout value corresponding to a master of the second master group.

Abstract: A mobile System on Chip (SoC) including a central processing unit (CPU) and an audio out module that includes a buffer and an audio interface. A power mode of the audio out module is controlled separately from a power mode of the mobile SoC so that the audio out module operates when the mobile SoC is in a power down mode.

Abstract: A method of operating a semiconductor memory device includes receiving a timeout index signal corresponding to a master of the first master group based on a residual capacity of a data buffer of the first master, setting a first timeout value in response to the timeout index signal, and changing an execution order of commands stored in a queue of the semiconductor memory device based on a result of counting the first timeout value and counting a second timeout value corresponding to a master of the second master group.

Abstract: A method of operating a semiconductor memory device includes receiving a timeout index signal corresponding to a master of the first master group based on a residual capacity of a data buffer of the first master, setting a first timeout value in response to the timeout index signal, and changing an execution order of commands stored in a queue of the semiconductor memory device based on a result of counting the first timeout value and counting a second timeout value corresponding to a master of the second master group.

Abstract: A buffer memory for rotating an image. The buffer memory is address-mapped in three dimensions including a first axis, a second axis, and a third axis, that are orthogonal to one another. Data may be sequentially accessed (read from or written to) the buffer memory in each of the direction of the first axis, the direction of the second axis, and the direction of the third direction. Second data may written to a given plane of the buffer memory at the same time that first data is read from the same plane of the buffer memory.

Abstract: A mobile System on Chip (SoC) including a central processing unit (CPU) and an audio out module that includes a buffer and an audio interface. A power mode of the audio out module is controlled separately from a power mode of the mobile SoC so that the audio out module operates when the mobile SoC is in a power down mode.

Abstract: A system timer including a divider unit configured to fractionally divide a first clock signal and output a second clock signal having an asymmetric duty ratio and an interrupt generation unit configured to count a cycle of the second clock signal and output an interrupt signal according to the count.

Abstract: A mobile System on Chip (SoC) including a central processing unit (CPU) and an audio out module that includes a buffer and an audio interface. A power mode of the audio out module is controlled separately from a power mode of the mobile SoC so that the audio out module operates when the mobile SoC is in a power down mode.

Abstract: A bus arbiter includes an arbitration stop determining unit and a transaction arbitrating unit. The arbitration stop determining unit generates an arbitration stop signal based upon transaction grouping request signals which indicate whether successive transactions are requested. The transaction arbitrating unit selectively performs an arbitration operation based upon the arbitration stop signal.

Abstract: A system timer including a divider unit configured to fractionally divide a first clock signal and output a second clock signal having an asymmetric duty ratio and an interrupt generation unit configured to count a cycle of the second clock signal and output an interrupt signal according to the count.

Abstract: A buffer memory for rotating an image. The buffer memory is address-mapped in three dimensions including a first axis, a second axis, and a third axis, that are orthogonal to one another. Data may be sequentially accessed (read from or written to) the buffer memory in each of the direction of the first axis, the direction of the second axis, and the direction of the third direction. Second data may written to a given plane of the buffer memory at the same time that first data is read from the same plane of the buffer memory.

Abstract: A mobile System on Chip (SoC) including a central processing unit (CPU) and an audio out module that includes a buffer and an audio interface. A power mode of the audio out module is controlled separately from a power mode of the mobile SoC so that the audio out module operates when the mobile SoC is in a power down mode.