Patents by Inventor Eun-Ae Chung

Eun-Ae Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240079557
    Abstract: An anode active material for a secondary battery according to an embodiment of the present application includes lithium-silicon composite oxide particle. The lithium-silicon composite oxide particles include at least one selected from the group consisting of Li2SiO3 and Li2Si2O5 and have a phase fraction ratio defined by Equation 1 of 1.0 or less. A content of particles having a diameter of less than 3 ?m is 5 vol % or less based on a total volume of the lithium-silicon composite oxide particles.
    Type: Application
    Filed: March 23, 2023
    Publication date: March 7, 2024
    Inventors: Joon Hyung MOON, Eun Jun PARK, Do Ae YU, Ju Ho CHUNG
  • Patent number: 9564435
    Abstract: A semiconductor device includes a substrate having a logic device region including logic devices thereon, and an input/output (I/O) device region including I/O devices thereon adjacent the logic device region. A first fin field-effect transistor (FinFET) on the logic device region includes a first semiconductor fin protruding from the substrate, and a triple-gate structure having a first gate dielectric layer and a first gate electrode thereon. A second FinFET on the I/O device region includes a second semiconductor fin protruding from the substrate, and a double-gate structure having a second gate dielectric layer and a second gate electrode thereon. The first and second gate dielectric layers have different thicknesses. Related devices and fabrication methods are also discussed.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: February 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-ae Chung, Jung-dal Choi, Toshiro Nakanishi, Yu-bin Kim, Gab-jin Nam, Dong-kyu Lee, Guangfan Jiao
  • Patent number: 9443735
    Abstract: There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate having an active region; forming a dielectric layer for gate insulation on the active region; forming a curing layer with a material containing germanium (Ge) on the dielectric layer; heat-treating the curing layer; and removing the curing layer. The germanium-containing material may be silicon germanium (SiGe) or germanium (Ge).
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: September 13, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Soak Kim, Gab Jin Nam, Dong Hwan Kim, Su Hwan Kim, Toshiro Nakanishi, Sung Kweon Baek, Tae Hyun An, Eun Ae Chung
  • Patent number: 9368589
    Abstract: A semiconductor device includes a first source/drain region and a second source/drain region disposed in an active region of a semiconductor substrate, and a gate structure crossing the active region and disposed between the first and second source/drain regions, the gate structure including a gate electrode having a first part and a second part on the first part, the gate electrode being at a lower level than an upper surface of the active region, an insulating capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an empty space between the active region and the second part of the gate electrode.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: June 14, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Kweon Baek, Gab-Jin Nam, Jin-Soak Kim, Ji-Young Min, Eun-Ae Chung
  • Publication number: 20160104705
    Abstract: A semiconductor device includes a substrate having a logic device region including logic devices thereon, and an input/output (I/O) device region including I/O devices thereon adjacent the logic device region. A first fin field-effect transistor (FinFET) on the logic device region includes a first semiconductor fin protruding from the substrate, and a triple-gate structure having a first gate dielectric layer and a first gate electrode thereon. A second FinFET on the I/O device region includes a second semiconductor fin protruding from the substrate, and a double-gate structure having a second gate dielectric layer and a second gate electrode thereon. The first and second gate dielectric layers have different thicknesses. Related devices and fabrication methods are also discussed.
    Type: Application
    Filed: June 29, 2015
    Publication date: April 14, 2016
    Inventors: Eun-ae Chung, Jung-dal Choi, Toshiro Nakanishi, Yu-bin Kim, Gab-jin Nam, Dong-kyu Lee, Guangfan Jiao
  • Publication number: 20150228722
    Abstract: Provided is a semiconductor device including: a substrate; a first fin-field effect transistor comprising a first fin-type semiconductor layer having a first height and a first width, formed on the substrate; and a second fin-field effect transistor comprising a second fin-type semiconductor layer having a second height and a second width, formed on the substrate. The first fin-field effect transistor and the second fin-field effect transistor are separated by a predetermined distance. The first height is greater than the second height and the first width is less than the second width.
    Type: Application
    Filed: February 3, 2015
    Publication date: August 13, 2015
    Inventors: Eun-Ae CHUNG, Gab-Jin NAM, Sung-Min KIM, Sung-Kweon BAEK, Jin-Soak KIM
  • Publication number: 20150132937
    Abstract: There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate having an active region; forming a dielectric layer for gate insulation on the active region; forming a curing layer with a material containing germanium (Ge) on the dielectric layer; heat-treating the curing layer; and removing the curing layer. The germanium-containing material may be silicon germanium (SiGe) or germanium (Ge).
    Type: Application
    Filed: July 28, 2014
    Publication date: May 14, 2015
    Inventors: Jin Soak Kim, Gab Jin Nam, Dong Hwan Kim, Su Hwan Kim, Toshiro Nakanishi, Sung Kweon Baek, Tae Hyun An, Eun Ae Chung
  • Publication number: 20140291755
    Abstract: A semiconductor device includes a first source/drain region and a second source/drain region disposed in an active region of a semiconductor substrate, and a gate structure crossing the active region and disposed between the first and second source/drain regions, the gate structure including a gate electrode having a first part and a second part on the first part, the gate electrode being at a lower level than an upper surface of the active region, an insulating capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an empty space between the active region and the second part of the gate electrode.
    Type: Application
    Filed: January 29, 2014
    Publication date: October 2, 2014
    Inventors: Sung-Kweon BAEK, Gab-Jin NAM, Jin-Soak KIM, Ji-Young MIN, Eun-Ae CHUNG
  • Publication number: 20140035058
    Abstract: Methods of manufacturing a semiconductor device include forming a thin layer on a substrate including a first region and a second region and forming a gate insulating layer on the thin layer. A lower electrode layer is formed on the gate insulating layer and the lower electrode layer disposed in the second region is removed to expose the gate insulating layer in the second region. Nitrogen is doped into an exposed portion of the gate insulating layer and the thin layer disposed under the gate insulating layer. An upper electrode layer is formed on the lower electrode layer remaining in the first region and the exposed portion of the gate insulating layer. The upper electrode layer, the lower electrode layer, the gate insulating layer and the thin layer are partially removed to form first and second gate structures in the first and second regions. The process may be simplified.
    Type: Application
    Filed: July 12, 2013
    Publication date: February 6, 2014
    Inventors: Ji-Young Min, Gab-Jin Nam, Eun-Ae Chung, Jung-Dal Choi, Jin-Soak Kim, Sung-Kweon Baek
  • Patent number: 8119486
    Abstract: A method according to example embodiments includes forming isolation regions in a substrate, the isolation regions defining active regions. Desired regions of the active regions and the isolation regions are removed, thereby forming recess channel trenches to a desired depth. The recess channel trenches are fog to have a first region in contact with the active regions and a second region in contact with the isolation regions. A width of a bottom surface of the recess channel trenches is less than that of a top surface thereof. The active regions and the isolation regions are annealed to uplift the bottom surface of the recess channel trenches. An area of the bottom surface of the first region is increased. A depth of the bottom surface of the first region is reduced.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: February 21, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Pil Kim, Eun-Ae Chung, Gab-Jin Nam, Hee-Don Hwang, Ji-Young Min
  • Patent number: 8110473
    Abstract: A semiconductor device including a multilayer dielectric film and a method for fabricating the semiconductor device are disclosed. The multilayer dielectric film includes a type-one dielectric film having a tetragonal crystalline structure, wherein the type-one dielectric film comprises a first substance. The multilayer dielectric film also comprises a type-two dielectric film also having a tetragonal crystalline structure, wherein the type-two dielectric film comprises a second substance different from the first substance and a dielectric constant of the type-two dielectric film is greater than a dielectric constant of the type-one dielectric film.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: February 7, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-yeol Kang, Jong-cheol Lee, Ki-vin Lim, Hoon-sang Choi, Eun-ae Chung
  • Publication number: 20110201168
    Abstract: A method according to example embodiments includes forming isolation regions in a substrate, the isolation regions defining active regions. Desired regions of the active regions and the isolation regions are removed, thereby forming recess channel trenches to a desired depth. The recess channel trenches are fog to have a first region in contact with the active regions and a second region in contact with the isolation regions. A width of a bottom surface of the recess channel trenches is less than that of a top surface thereof. The active regions and the isolation regions are annealed to uplift the bottom surface of the recess channel trenches. An area of the bottom surface of the first region is increased. A depth of the bottom surface of the first region is reduced.
    Type: Application
    Filed: January 4, 2011
    Publication date: August 18, 2011
    Inventors: Young-Pil Kim, Eun-Ae Chung, Gab-Jin Nam, Hee-Don Hwang, Ji-Young Min
  • Patent number: 7939872
    Abstract: A multi-dielectric film including at least one first dielectric film that is a composite film made of zirconium-hafnium-oxide and at least one second dielectric film that is a metal oxide film made of amorphous metal oxide. Adjacent ones of the dielectric films are made of different materials.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: May 10, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Cheol Lee, Sang-Yeol Kang, Ki-Vin Lim, Hoon-Sang Choi, Eun-Ae Chung
  • Patent number: 7838438
    Abstract: A dielectric layer, an MIM capacitor, a method of manufacturing the dielectric layer and a method of manufacturing the MIM capacitor. The method of manufacturing the dielectric layer includes chemically reacting a metal source with different amounts of an oxidizing agent based on the cycle of the chemical reactions in order to control leakage characteristics of the dielectric layer, the electrical characteristics of the dielectric layer, and the dielectric characteristics of the dielectric layer.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: November 23, 2010
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Ki Vin Im, Jae Hyun Yeo, Kyoung Ryul Yoon, Jong Cheol Lee, Eun Ae Chung, Young Sun Kim
  • Patent number: 7824501
    Abstract: Provided is an in-situ method of cleaning a vaporizer of an atomic layer deposition apparatus during a dielectric layer deposition process, to prevent nozzle blocking in the vaporizer and an atomic layer deposition apparatus. During the dielectric layer deposition process, the following steps are repeated: supplying a first source gas for dielectric layer deposition into a chamber of an atomic layer deposition apparatus; purging the first source gas; supplying a second source gas into the chamber of the atomic layer deposition apparatus; purging the second source gas, the in-situ method of cleaning the vaporizer is performed after supplying the first source gas for dielectric layer deposition and before supplying the first source gas again.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: November 2, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoon-sang Choi, Jong-cheol Lee, Ki-vin Im, Eun-ae Chung, Sang-yeol Kang, Young-sun Kim, Kwang-hee Lee
  • Publication number: 20100255651
    Abstract: A semiconductor device including a multilayer dielectric film and a method for fabricating the semiconductor device are disclosed. The multilayer dielectric film includes a type-one dielectric film having a tetragonal crystalline structure, wherein the type-one dielectric film comprises a first substance. The multilayer dielectric film also comprises a type-two dielectric film also having a tetragonal crystalline structure, wherein the type-two dielectric film comprises a second substance different from the first substance and a dielectric constant of the type-two dielectric film is greater than a dielectric constant of the type-one dielectric film.
    Type: Application
    Filed: December 10, 2009
    Publication date: October 7, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-yeol KANG, Jong-cheol LEE, Ki-vin LIM, Hoon-sang CHOI, Eun-ae CHUNG
  • Patent number: 7791125
    Abstract: A method of forming a semiconductor device includes loading a semiconductor substrate into a reaction chamber, and providing metal organic precursors including hafnium and zirconium into the reaction chamber to form hafnium-zirconium oxide (HfxZr1-xO; 0<X<1) with a tetragonal crystalline structure on the semiconductor substrate. Related structures are also discussed.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: September 7, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoon-Sang Choi, Jong-Cheol Lee, Ki-Vin Im, Jae-Hyun Yeo, Eun-Ae Chung, Sang-Yeol Kang
  • Patent number: 7759718
    Abstract: A method of forming a dielectric layer in a capacitor adapted for use in a semiconductor device is disclosed. The method includes forming a first ZrO2 layer, forming an interfacial layer using a plasma treatment on the first ZrO2 layer, and forming a second ZrO2 layer on the interfacial layer.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: July 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-yeol Kang, Jong-cheol Lee, Ki-vin Im, Jae-hyun Yeo, Hoon-sang Choi, Eun-ae Chung
  • Patent number: 7750385
    Abstract: A semiconductor device includes a lower electrode of a capacitor, a dielectric layer disposed on the lower electrode, and an upper electrode of the capacitor disposed on the dielectric layer. The upper electrode includes a doped poly-Si1-xGex layer. An interlayer insulating layer is disposed on the doped poly-Si1-xGex layer and has a contact hole partially exposing the doped poly-Si1-xGex layer. A metal contact plug is in the contact hole and an interconnection layer is disposed on the interlayer insulating layer and connected to the metal contact plug. Related interconnection structures and fabrication methods are also disclosed.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: July 6, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-ae Chung, Ki-sun Kim, Young-sun Kim, Jin-tae Noh
  • Publication number: 20100117194
    Abstract: A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first and second conductive layers and is a different material than the first and second conductive layers. The dielectric layer is on the lower electrode. The upper electrode is on the dielectric layer opposite to the lower electrode. The first and second conductive layers can have the same thickness. The chemical barrier layer can be thinner than each of the first and second conductive layers. Related methods are discussed.
    Type: Application
    Filed: December 16, 2009
    Publication date: May 13, 2010
    Inventors: Eun-ae Chung, Jae-hyoung Choi, Jung-hee Chung, Young-sun Kim, Cha-young Yoo