Patents by Inventor Eun-Chul Ahn

Eun-Chul Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8344497
    Abstract: A semiconductor package may include a semiconductor chip, a molding layer which molds the semiconductor chip, and an interconnection which extends crossing an interface between the semiconductor chip and the molding layer and connects the semiconductor chip to an outside, wherein a shape of the interconnection is changed along the extended length thereof. According to the present invention, even if a mechanical stress or a thermal stress is applied to an interconnection, a crack does not occur in the interconnection or the interconnection is not disconnected. Therefore, a reliability of the semiconductor package is improved.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: January 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pyoung-Wan Kim, Eun-Chul Ahn, Teak-Hoon Lee, Chul-Yong Jang
  • Publication number: 20120129333
    Abstract: Provided are a method for manufacturing a semiconductor package and a semiconductor package manufactured using the method. The method includes providing a substrate having a first region and a second region having a higher step difference than the first region, i.e., having a difference in height, forming a mask pattern having a first opening exposing a portion of the first region and a second opening exposing a portion of the second region on the substrate, forming first and second bump material films filling the first and second openings, respectively, and forming the first and second bumps by performing a reflow process on the first and second bump material films, wherein the first opening has a lower portion having the same width with the second opening and a top portion having a width greater than the second opening.
    Type: Application
    Filed: September 23, 2011
    Publication date: May 24, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-Young YIM, Eun-Chul AHN, Ui-Hyoung LEE, Moon-Gi CHO, Hwan-Sik LIM
  • Patent number: 8129221
    Abstract: Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in direct contact with the first semiconductor chip.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: March 6, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn
  • Publication number: 20110294260
    Abstract: Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in direct contact with the first semiconductor chip.
    Type: Application
    Filed: August 2, 2011
    Publication date: December 1, 2011
    Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn
  • Publication number: 20110244634
    Abstract: A semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package includes a first package that a first semiconductor chip is mounted on a front side of a first substrate and a redistributed pad including a first redistributed pad electrically connected to the first substrate and a second redistributed pad electrically connected to the first redistributed pad is disposed on the first semiconductor chip and a second package that a second semiconductor chip is mounted on a front side of a second substrate, the second package including a connection member electrically connected to the second redistributed pad. The connection member electrically connected to the redistributed pad electrically connects the first and second packages to each other.
    Type: Application
    Filed: May 9, 2011
    Publication date: October 6, 2011
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Young-Lyong Kim, Jong-Ho Lee, Cheul-Joong Youn, Eun-Chul Ahn
  • Patent number: 8022555
    Abstract: Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in direct contact with the first semiconductor chip.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: September 20, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn
  • Patent number: 8008771
    Abstract: A semiconductor chip package including a semiconductor chip including a first surface having bonding pads, a second surface facing the first surface, and sidewalls; a molding extension part surrounding the second surface and the sidewalls of the semiconductor chip; redistribution patterns extending from the bonding pads over the molding extension part, and electrically connected to the bonding pads; bump solder balls on the redistribution patterns; and a molding layer configured to cover the first surface of the semiconductor chip and the molding extension part, while exposing portions of each of the bump solder balls. The molding layer has concave meniscus surfaces between the bump solder balls adjacent to each other.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: August 30, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pyoung-Wan Kim, Eun-Chul Ahn, Jong-Ho Lee, Teak-Hoon Lee, Chul-Yong Jang
  • Publication number: 20110171781
    Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having an active surface, thinning the substrate by removing material from a second surface of the substrate opposite the active surface, bonding a metal carrier to the second surface of the thinned substrate, forming a via opening in the thinned substrate, forming a conductive member in the via opening, and patterning the metal carrier bonded to the second surface of the thinned substrate to form a metal pattern.
    Type: Application
    Filed: March 23, 2011
    Publication date: July 14, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong Ho LEE, Dong Ho LEE, Eun Chul AHN, Yong Chai KWON
  • Patent number: 7923291
    Abstract: A method of fabricating an electronic device having stacked chips is provided. The method includes forming a plurality of chips arranged in a row direction and at least one chip arranged in a column direction. A molding layer is formed between the chips. Grooves are formed in the molding layer between the chips arranged in the row direction. Conductive interconnections are formed on the substrate having the grooves. The substrate is sawn along an odd- or even-numbered one of the grooves to be separated into a plurality of unit substrates. At least one of the separated unit substrates is folded along an unsawn groove of the grooves.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: April 12, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hae-Jung Yu, Eun-Chul Ahn, Tae-Gyeong Chung, Nam-Seog Kim
  • Publication number: 20110079897
    Abstract: In an integrated circuit (IC) chip and a flip chip package having the same, no wiring line is provided and the first electrode pad does not make contact with the wiring line in a pad area of the IC chip. Thus, the first bump structure makes contact with the first electrode regardless of the wiring line in the pad area. The second electrode pad makes contact with the wiring line in a pseudo pad area of the IC chip. Thus, the second bump structure in the pseudo pad area makes contact with an upper surface of the second electrode at a contact point(s) spaced apart from the wiring line under the second electrode.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 7, 2011
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Jin-Woo PARK, Eun-Chul Ahn, Dong-Kil Shin, Sun-Won Kang, Jong-Ho Lee
  • Patent number: 7915710
    Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having an active surface, thinning the substrate by removing material from a second surface of the substrate opposite the active surface, bonding a metal carrier to the second surface of the thinned substrate, forming a via opening in the thinned substrate, forming a conductive member in the via opening, and patterning the metal carrier bonded to the second surface of the thinned substrate to form a metal pattern.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: March 29, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Ho Lee, Dong Ho Lee, Eun Chul Ahn, Yong Chai Kwon
  • Patent number: 7898075
    Abstract: In one embodiment, a semiconductor package disclosed herein can be generally characterized as including a resin substrate having a first recess, a first interconnection disposed on a surface of the first recess, a first semiconductor chip disposed in the first recess, and an underfill resin layer substantially filling the first recess and covering a side surface of the first semiconductor chip. The first semiconductor chip is electrically connected to the first interconnection.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: March 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul-Yong Jang, Eun-Chul Ahn, Pyoung-Wan Kim, Taek-Hoon Lee
  • Patent number: 7888785
    Abstract: A device includes a base substrate, a package including an encapsulated die, the package at least partially embedded in the base substrate, and a wiring portion on the package and extending across at least a portion of the base substrate adjacent to the package.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: February 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Chul Ahn, Min-Ho O, Jong Ho Lee
  • Publication number: 20100327439
    Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.
    Type: Application
    Filed: September 3, 2010
    Publication date: December 30, 2010
    Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn
  • Patent number: 7821139
    Abstract: A flip-chip assembly comprises a semiconductor chip, a substrate, a first buffer layer, a second buffer layer and a conductive bump. The semiconductor chip includes a first region and a second region adjacent to the first region. The substrate is disposed under the semiconductor chip. The first buffer layer is disposed between the first region of the semiconductor chip and the substrate. The second buffer layer is disposed between the second region of the semiconductor chip and the substrate. The conductive bump is formed through the second buffer layer and electrically connects the semiconductor chip to the substrate.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: October 26, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Joo Hwang, Eun-Chul Ahn, Tae-Gyeong Chung
  • Publication number: 20100237491
    Abstract: A semiconductor package may include a semiconductor chip having a plurality of chip pads arranged apart from each other on a substrate body and an insulation layer having chip pad-exposing portions for exposing chip pads. The insulation layer may be separated by underlying layer-exposing portions between the chip pads, and the semiconductor package may further include a connector in the chip pad-exposing portions and connected to corresponding chip pads.
    Type: Application
    Filed: October 30, 2009
    Publication date: September 23, 2010
    Inventors: Jin-woo Park, Eun-chul Ahn
  • Publication number: 20100213593
    Abstract: A stacked semiconductor package includes an upper unit package and a lower unit package. The lower unit package includes a substrate, a semiconductor chip disposed on an upper surface of the substrate, terminal pads arranged on an upper surface of the semiconductor chip, protrusions formed on the terminal pads, a protective layer formed on the substrate and covering the semiconductor chip and the protrusions, and openings formed in the protective layer and exposing the protrusions. The upper unit package includes a substrate, ball lands provided on a lower surface of the substrate, and solder balls formed on the ball lands. The solder balls of the upper unit package are inserted into the openings of the lower unit package to be connected to the protrusions of the lower unit package.
    Type: Application
    Filed: February 23, 2010
    Publication date: August 26, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Byung-Woo LEE, Young-Lyong Kim, Eun-Chul Ahn
  • Publication number: 20100078819
    Abstract: A semiconductor device including an interconnection structure including a copper pad, a pad barrier layer and a metal redistribution layer, an interconnection structure thereof and methods of fabricating the same are provided. The semiconductor device includes a copper pad disposed on a first layer, a pad barrier layer including titanium disposed on the copper pad, an inorganic insulating layer disposed on the pad barrier layer, a buffer layer disposed on the inorganic insulating layer, wherein the inorganic insulating layer and the buffer layer expose a portion of the pad barrier layer, a seed metal layer disposed on the exposed buffer layer, a metal redistribution layer disposed on the seed metal layer, and a first protective layer disposed on the metal redistribution layer.
    Type: Application
    Filed: September 28, 2009
    Publication date: April 1, 2010
    Inventors: Chang-Woo SHIN, Hyun-Soo Chung, Eun-Chul Ahn, Jum-Gon Kim, Jin-Ho Chun
  • Publication number: 20100022051
    Abstract: A method of fabricating an electronic device having stacked chips is provided. The method includes forming a plurality of chips arranged in a row direction and at least one chip arranged in a column direction. A molding layer is formed between the chips. Grooves are formed in the molding layer between the chips arranged in the row direction. Conductive interconnections are formed on the substrate having the grooves. The substrate is sawn along an odd- or even-numbered one of the grooves to be separated into a plurality of unit substrates. At least one of the separated unit substrates is folded along an unsawn groove of the grooves.
    Type: Application
    Filed: July 28, 2009
    Publication date: January 28, 2010
    Inventors: Hae-Jung Yu, Eun-Chul Ahn, Tae-Gyeong Chung, Nam-Seog Kim
  • Publication number: 20090309206
    Abstract: A semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package includes a first package that a first semiconductor chip is mounted on a front side of a first substrate and a redistributed pad including a first redistributed pad electrically connected to the first substrate and a second redistributed pad electrically connected to the first redistributed pad is disposed on the first semiconductor chip and a second package that a second semiconductor chip is mounted on a front side of a second substrate, the second package including a connection member electrically connected to the second redistributed pad. The connection member electrically connected to the redistributed pad electrically connects the first and second packages to each other.
    Type: Application
    Filed: June 15, 2009
    Publication date: December 17, 2009
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Young-Lyong KIM, Jong-Ho LEE, Cheul-Joong YOUN, Eun-Chul AHN