Abstract: A semiconductor device includes a memory string coupled between a source line and a bit line and including a plurality of memory cells, a plurality of word lines, a peripheral circuit configured to apply a program voltage to a word line, apply a first pass voltage to a word line coupled to a first memory cell adjacent to the selected memory cell, and apply a second pass voltage to a second memory cell adjacent to the selected memory cell, and control logic configured to control the peripheral circuit so that the first pass voltage has a higher voltage level than the second pass voltage when a program target level of the selected memory cell is lower than a first threshold value, and the first pass voltage has a lower voltage level than the second pass voltage when the program target level is higher than a second threshold value.

Abstract: A semiconductor device includes a memory string coupled between a source line and a bit line and including a plurality of memory cells, a plurality of word lines, a peripheral circuit configured to apply a program voltage to a word line, apply a first pass voltage to a word line coupled to a first memory cell adjacent to the selected memory cell, and apply a second pass voltage to a second memory cell adjacent to the selected memory cell, and control logic configured to control the peripheral circuit so that the first pass voltage has a higher voltage level than the second pass voltage when a program target level of the selected memory cell is lower than a first threshold value, and the first pass voltage has a lower voltage level than the second pass voltage when the program target level is higher than a second threshold value.

Abstract: A semiconductor device includes a clock selection block selecting a first or a second input clock as a reference clock based on a phase detection signal; a clock generation circuit outputting first to Nth sampling clocks by distributing the reference clock to first to Nth clock paths, and outputting a first training signal by delaying a test pulse through one clock path during a training operation; a data input circuit sampling input data based on the first and second input clocks and one sampling clock outputted through the same clock path as the first training signal among the first to Nth sampling clocks; and a training circuit delaying the test pulse by a reference delay value to output a second training signal, and comparing a phase of the first training signal with a phase of the second training signal to generate the phase detection signal, during the training operation.

Abstract: The present invention relates to a kit for simultaneous diagnosis of viral respiratory diseases. To be more specific, the present invention is directed to a method for diagnosing viral respiratory diseases by detecting the genes specific to the respiratory disease-causing virus, a primer set for diagnosing the viral respiratory diseases used in the diagnosis method, a composition for simultaneous diagnosis of viral respiratory diseases, comprising the primer set, and a kit for simultaneous diagnosis of viral respiratory diseases, comprising the composition. When the primer set of the present invention for diagnosing the viral respiratory diseases is used, 14 different types of respiratory viruses can be simultaneously detected only with one reaction through real-time multiplex reverse transcription (RT)-PCR, and the onset of respiratory diseases caused by these viruses can be diagnosed. Thus, the primer set of the present invention can be widely used for prompt diagnosis and treatment of respiratory diseases.

Abstract: The present technique relates to an electronic device, and more particularly, to a semiconductor memory device and an operating method thereof. A semiconductor memory device having improved reliability includes an address decoder applying a program voltage to a selected word line coupled to selected memory cells, among the plurality of memory cells, and a read and write circuit applying a program permission voltage or a program inhibition voltage to bit lines coupled to the selected memory cells, and a control logic controlling the read and write circuit to sequentially apply the program permission voltage and the program inhibition voltage to the bit lines coupled to the selected memory cells when the program voltage is applied.

Abstract: Disclosed is a refrigerator having a shelf assembly in a storage compartment. The refrigerator includes a body provided with a storage compartment, a shelf configured to load goods stored in the storage compartment, a panel configured to form one surface of the storage compartment and provided with a plurality of support guides, and a frame configured to support the shelf and configured to be movable in a transverse direction along the plurality of support guides by being detachably coupled to the panel.

Abstract: The present technique relates to an electronic device, and more particularly, to a semiconductor memory device and an operating method thereof. A semiconductor memory device having improved reliability includes an address decoder applying a program voltage to a selected word line coupled to selected memory cells, among the plurality of memory cells, and a read and write circuit applying a program permission voltage or a program inhibition voltage to bit lines coupled to the selected memory cells, and a control logic controlling the read and write circuit to sequentially apply the program permission voltage and the program inhibition voltage to the bit lines coupled to the selected memory cells when the program voltage is applied.

Abstract: A semiconductor device according to an embodiment may include cell strings including a plurality of memory cells coupled between bit lines and a source line and coupled to word lines, a peripheral circuit suitable for programming selected memory cells coupled to a selected word line among the word lines by applying a program voltage to the selected word line, and applying one or more pass voltages to unselected word lines, and a control circuit suitable for controlling the peripheral circuit to temporarily float the unselected word lines while the selected memory cells are programmed.

Abstract: Provided are a 3-dimensional interface device through motion recognition and a control method thereof, and is a method of controlling an operation range and a movement speed of the interface device. The interface device includes a display unit which is a display unit, a control terminal generating an output signal output to the display unit and controlling drive of the display unit, and an interface unit connected to the control terminal, receiving a user's command from a user, and transmitting the user's command to the control terminal. The interface unit includes a detecting unit detecting a user's motion, and a control unit controlling drive of the interface unit.

Abstract: A method of manufacturing a semiconductor memory device includes forming a first attached layer on a substrate, forming a stack layer on the first attached layer, separating the stack layer and the first attached layer from each other, forming vertical holes by performing a first etch process on the stack layer in a direction from bottom to top, removing the first attached layer, attaching the stack layer in which the vertical holes are formed to the substrate, and performing a second etch process so that each of the vertical holes has a uniform width.

Abstract: Provided are a 3-dimensional interface device through motion recognition and a control method thereof, and is a method of controlling an operation range and a movement speed of the interface device. The interface device includes a display unit which is a display unit, a control terminal generating an output signal output to the display unit and controlling drive of the display unit, and an interface unit connected to the control terminal, receiving a user's command from a user, and transmitting the user's command to the control terminal. The interface unit includes a detecting unit detecting a user's motion, and a control unit controlling drive of the interface unit.

Abstract: The present invention relates to a kit for simultaneous diagnosis of viral respiratory diseases. To be more specific, the present invention is directed to a method for diagnosing viral respiratory diseases by detecting the genes specific to the respiratory disease-causing virus, a primer set for diagnosing the viral respiratory diseases used in the diagnosis method, a composition for simultaneous diagnosis of viral respiratory diseases, comprising the primer set, and a kit for simultaneous diagnosis of viral respiratory diseases, comprising the composition. When the primer set of the present invention for diagnosing the viral respiratory diseases is used, 14 different types of respiratory viruses can be simultaneously detected only with one reaction through real-time multiplex reverse transcription (RT)-PCR, and the onset of respiratory diseases caused by these viruses can be diagnosed. Thus, the primer set of the present invention can be widely used for prompt diagnosis and treatment of respiratory diseases.

Abstract: A phase-change memory device including a first contact region and a second contact region formed on a semiconductor substrate. A first insulating layer with a first contact hole and a second contact hole is disposed on the semiconductor substrate, exposing the first and second contact regions. A first conductive layer is disposed on the first insulating interlayer to fill the first and the second contact holes. A first protection layer pattern and a lower wiring protection pattern are disposed on the first conductive layer. A first contact with a first electrode and a second contact with a lower wiring are disposed so as to connect the first and second contact regions. A second protection layer with a second electrode is disposed on the first protection layer pattern and the lower wiring protection pattern. A via filled with a phase-change material is disposed between the first electrode and the second electrode.

Abstract: A device includes an insulating layer on a substrate having a lower conductive pattern, the insulating layer having a contact hole that penetrates the insulating layer and exposes a portion of the lower conductive pattern, a catalytic pattern having a first portion on the exposed portion of the lower conductive pattern and a second portion on a sidewall of the contact hole, a spacer on the sidewall of the contact hole, wherein the second portion of the catalytic pattern is disposed between the spacer and the sidewall, and a contact plug in the contact hole and contacting the catalytic pattern, the contact plug being a carbon nanotube material.

Abstract: In methods of manufacturing a variable resistance structure and a phase-change memory device, after forming a first insulation layer on a substrate having a contact region, a contact hole exposing the contact region is formed through the first insulation layer. After forming a first conductive layer on the first insulation layer to fill up the contact hole, a first protection layer pattern is formed on the first conductive layer. The first conductive layer is partially etched to form a contact and to form a pad on the contact. A second protection layer is formed on the first protection layer pattern, and then an opening exposing the pad is formed through the second protection layer and the first protection layer pattern. After formation of a first electrode, a phase-change material layer pattern and a second electrode are formed on the first electrode and the second protection layer.

Abstract: A device includes an insulating layer on a substrate having a lower conductive pattern, the insulating layer having a contact hole that penetrates the insulating layer and exposes a portion of the lower conductive pattern, a catalytic pattern having a first portion on the exposed portion of the lower conductive pattern and a second portion on a sidewall of the contact hole, a spacer on the sidewall of the contact hole, wherein the second portion of the catalytic pattern is disposed between the spacer and the sidewall, and a contact plug in the contact hole and contacting the catalytic pattern, the contact plug being a carbon nanotube material.

Abstract: A method of forming a ferroelectric layer is provided. A metal-organic source gas is provided into a chamber into which an oxidation gas is provided for a first time period to form ferroelectric grains on a substrate. A ferroelectric layer is formed by performing at least twice a step of providing a metal-organic source gas into the chamber during the first time period using a pulse method to grow the ferroelectric grains.

Abstract: In methods of manufacturing a variable resistance structure and a phase-change memory device, after forming a first insulation layer on a substrate having a contact region, a contact hole exposing the contact region is formed through the first insulation layer. After forming a first conductive layer on the first insulation layer to fill up the contact hole, a first protection layer pattern is formed on the first conductive layer. The first conductive layer is partially etched to form a contact and to form a pad on the contact. A second protection layer is formed on the first protection layer pattern, and then an opening exposing the pad is formed through the second protection layer and the first protection layer pattern. After formation of a first electrode, a phase-change material layer pattern and a second electrode are formed on the first electrode and the second protection layer.

Abstract: In methods of manufacturing a variable resistance structure and a phase-change memory device, after forming a first insulation layer on a substrate having a contact region, a contact hole exposing the contact region is formed through the first insulation layer. After forming a first conductive layer on the first insulation layer to fill up the contact hole, a first protection layer pattern is formed on the first conductive layer. The first conductive layer is partially etched to form a contact and to form a pad on the contact. A second protection layer is formed on the first protection layer pattern, and then an opening exposing the pad is formed through the second protection layer and the first protection layer pattern. After formation of a first electrode, a phase-change material layer pattern and a second electrode are formed on the first electrode and the second protection layer.

Abstract: In methods of manufacturing a variable resistance structure and a phase-change memory device, after forming a first insulation layer on a substrate having a contact region, a contact hole exposing the contact region is formed through the first insulation layer. After forming a first conductive layer on the first insulation layer to fill up the contact hole, a first protection layer pattern is formed on the first conductive layer. The first conductive layer is partially etched to form a contact and to form a pad on the contact. A second protection layer is formed on the first protection layer pattern, and then an opening exposing the pad is formed through the second protection layer and the first protection layer pattern. After formation of a first electrode, a phase-change material layer pattern and a second electrode are formed on the first electrode and the second protection layer.