Abstract: The present invention provides a novel angiogenesis inhibitor, LK68 whose amino acid sequence is identical with the human apolipoprotein (a) kringle domains IV36, IV37 and V38, a cDNA sequence encoding the LK68, a recombinant expression vector comprising the cDNA, a recombinant microorganism transformed with the recombinant expression vector and a novel use of the LK68 as an anticancer agent and a method for treating angiogenesis-mediated disease. LK68, LK6, LK7 and LK8 exhibit inhibitory activities on the cultured endothelial cell proliferation as well as on the endothelial cell migration. LK68 and its single kringles also inhibit the normal development of capillaries in the chick embryo chorioallantoic membrane (CAM). It was also showed that systemic administration of LK68 causes the inhibition of primary tumor growth, which is correlated with a suppression of tumor-induced angiogenesis.

Abstract: A semiconductor device in which polysilicon is used to form source and drain regions in an initial process step so as to reduce resistance of bit lines and minimize a junction capacitance and thus improve its reliability, and a method for fabricating the same are disclosed, the semiconductor device including a semiconductor substrate, trenches formed in predetermined areas of the semiconductor substrate, an insulating layer formed in the trenches and beneath a surface of the substrate to have a recess, a polysilicon layer formed on the insulating layer in the trench, source and drain regions formed at both sides of the polysilicon layer beneath a surface of the semiconductor substrate, and gates formed over the semiconductor substrate.

Abstract: A semiconductor device in which polysilicon is used to form source and drain regions in an initial process step so as to reduce resistance of bit lines and minimize a junction capacitance and thus improve its reliability, and a method for fabricating the same are disclosed, the semiconductor device including a semiconductor substrate, trenches formed in predetermined areas of the semiconductor substrate, an insulating layer formed in the trenches and beneath a surface of the substrate to have a recess, a polysilicon layer formed on the insulating layer in the trench, source and drain regions formed at both sides of the polysilicon layer beneath a surface of the semiconductor substrate, and gates formed over the semiconductor substrate.

Abstract: A method of fabricating a flash memory cell includes the steps of forming a field insulating layer on a substrate, forming a first gate oxide layer on the substrate, forming a floating gate, a first insulating layer and a control gate on the first gate oxide layer, forming sidewall insulating layers at both sides of the floating gate and the control gate, forming sidewall conductive layers on the sidewall insulating layers, and forming a source and drain region in the substrate.

Abstract: A semiconductor device in which polysilicon is used to form source and drain regions in an initial process step so as to reduce resistance of bit lines and minimize a junction capacitance and thus improve its reliability, and a method for fabricating the same are disclosed, the semiconductor device including a semiconductor substrate, trenches formed in predetermined areas of the semiconductor substrate, an insualting layer formed in the trenches and beneath a surface of the substrate to have a recess, a polysilicon layer formed on the insualting layer in the trench, source and drain regions formed at both sides of the polysilicon layer beneath a surface of the semiconductor substrate, and gates formed over the semiconductor substrate.

Abstract: A flash memory is disclosed including a second conductivity-type substrate having first conductivity-type first and second impurity regions spaced apart from each other by a predetermined distance; a second conductivity-type floating gate formed above part of the first impurity region; a first conductivity-type floating gate formed over the second conductivity-type floating gate; and an insulating layer and first conductivity-type control gate sequentially formed on the first conductivity-type floating gate.

Abstract: A flash memory cell includes a semiconductor substrate, source and drain regions in the semiconductor substrate, a channel region having first and second channel region between the source and drain regions, a field oxide layer at a field region of the semiconductor substrate, a first gate oxide layer on the semiconductor substrate including the source and rain regions, a floating gate having first and second sides on the first gate oxide layer, a first insulating layer having first and second sides on the floating gate, a control gate having first and second sides on the first insulating layer, a second insulating layer having first and second sides on the control gate, a third insulating layer on the second sides of the second insulating layer including the control gate and the first insulating layer, a fourth insulating layer on the second side of the floating gate and the first sides of the second insulating layer including the control gate and the first insulating layer, a selection gate on the fifth insu

Abstract: A flash memory is disclosed including a second conductivity-type substrate having first conductivity-type first and second impurity regions spaced apart from each other by a predetermined distance; a second conductivity-type floating gate formed above part of the first impurity region; a first conductivity-type floating gate formed over the second conductivity-type floating gate; and an insulating layer and first conductivity-type control gate sequentially formed on the first conductivity-type floating gate.