Patents by Inventor Eun-ji Jung

Eun-ji Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10418326
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film on a substrate, the interlayer insulating film including an opening, a barrier conductive film extending along a sidewall of the opening and a bottom surface exposed by the opening, a first film disposed on the barrier conductive film and in the opening, and the first film including cobalt, and a conductive liner on the barrier conductive film, the conductive liner extending along a portion of a side all of the opening and including a metal other than cobalt.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: September 17, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun Ji Jung, Rak Hwan Kim, Byung Hee Kim, Young Hun Kim, Gyeong Yun Han
  • Patent number: 10388563
    Abstract: A semiconductor device includes a lower layer, an upper layer on the lower layer, a contact between the lower layer and the upper layer, the contact electrically connects the lower layer and the upper layer, a capping pattern wrapping around the contact and covering an upper surface of the contact, a barrier layer wrapping around the capping pattern and covering a lower surface of the capping pattern and a lower surface of the contact, and an interlayer insulating layer between the lower layer and the upper layer, the interlayer insulating layer wrapping around the barrier layer and exposing an upper surface of the capping pattern, wherein the capping pattern includes a material having an etching selectivity with respect to an oxide.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: August 20, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Rak Hwan Kim, Byung Hee Kim, Sang Bom Kang, Jong Jin Lee, Eun Ji Jung
  • Publication number: 20190189744
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Application
    Filed: February 13, 2019
    Publication date: June 20, 2019
    Inventors: Jin-Nam Kim, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
  • Patent number: 10304734
    Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 28, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo Kyung You, Jong Min Baek, Sang Shin Jang, Byung Hee Kim, Vietha Nguyen, Nae In Lee, Woo Jin Lee, Eun Ji Jung, Kyu Hee Han
  • Patent number: 10245533
    Abstract: Disclosed is a pore adjusting filtering apparatus including: a cylinder having a plurality of holes and in which a screw is rotatably installed; an endless track coupled to an outer peripheral surface of the cylinder by a cylinder, an endless track pin, and a support to be rotatable together with the cylinder; a fiber yarn bundle support rod inserted into the endless track to be connected to the endless track; a fiber yarn bundle, one end of which is fitted with and supported by the fiber yarn bundle support rod; a fiber yarn bundle support net for supporting the fiber yarn bundle while being attached to an outer peripheral surface of the fiber yarn bundle; a cleaning separator fixedly installed at an upper outer side of the cylinder; and an ejector installed on an upper outer side of the cylinder.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: April 2, 2019
    Assignees: Yoonjin Environment Co., Inc.
    Inventors: Jung-A Rhim, Jin-Gon Yoon, Jeong-Hyo Yoon, Je-Sung Ahn, Jong-Won Kim, Jang-Gon Im, Hyen-Woo Kim, Eun-Joo Shin, Sang-Hee Kim, Jeong-Hoon Im, Eun-Ji Jung
  • Patent number: 10217820
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: February 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Nam Kim, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
  • Publication number: 20180330987
    Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.
    Type: Application
    Filed: July 26, 2018
    Publication date: November 15, 2018
    Inventors: WOO KYUNG YOU, JONG MIN BAEK, SANG SHIN JANG, BYUNG HEE KIM, VIETHA NGUYEN, NAE IN LEE, WOO JIN LEE, EUN JI JUNG, KYU HEE HAN
  • Patent number: 10062609
    Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 28, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo Kyung You, Jong Min Baek, Sang Shin Jang, Byung Hee Kim, Vietha Nguyen, Nae In Lee, Woo Jin Lee, Eun Ji Jung, Kyu Hee Han
  • Publication number: 20180166334
    Abstract: A semiconductor device includes a lower layer, an upper layer on the lower layer, a contact between the lower layer and the upper layer, the contact electrically connects the lower layer and the upper layer, a capping pattern wrapping around the contact and covering an upper surface of the contact, a barrier layer wrapping around the capping pattern and covering a lower surface of the capping pattern and a lower surface of the contact, and an interlayer insulating layer between the lower layer and the upper layer, the interlayer insulating layer wrapping around the barrier layer and exposing an upper surface of the capping pattern, wherein the capping pattern includes a material having an etching selectivity with respect to an oxide.
    Type: Application
    Filed: August 3, 2017
    Publication date: June 14, 2018
    Inventors: Rak Hwan KIM, Byung Hee KIM, Sang Bom KANG, Jong Jin LEE, Eun Ji JUNG
  • Publication number: 20180158781
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film on a substrate, the interlayer insulating film including an opening, a barrier conductive film extending along a sidewall of the opening and a bottom surface exposed by the opening, a first film disposed on the barrier conductive film and in the opening, and the first film including cobalt, and a conductive liner on the barrier conductive film, the conductive liner extending along a portion of a side all of the opening and including a metal other than cobalt.
    Type: Application
    Filed: December 6, 2017
    Publication date: June 7, 2018
    Inventors: Eun Ji Jung, Rak Hwan Kim, Byung Hee Kim, Young Hun Kim, Gyeong Yun Han
  • Patent number: 9991203
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film, a first trench having a first width, and a second trench having a second width, the second trench including an upper portion and a lower portion, the second width being greater than the first width, a first wire substantially filling the first trench and including a first metal, and a second wire substantially filling the second trench and including a lower wire and an upper wire, the lower wire substantially filling a lower portion of the second trench and including the first metal, and the upper wire substantially filling an upper portion of the second trench and including a second metal different from the first metal.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: June 5, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Rak-Hwan Kim, Byung-Hee Kim, Jin-Nam Kim, Jong-Min Baek, Nae-In Lee, Eun-Ji Jung
  • Publication number: 20180033691
    Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.
    Type: Application
    Filed: December 29, 2016
    Publication date: February 1, 2018
    Inventors: Woo Kyung You, JONG MIN BAEK, SANG SHIN JANG, BYUNG HEE KIM, VIETHA NGUYEN, NAE IN LEE, WOO JIN LEE, EUN JI JUNG, KYU HEE HAN
  • Publication number: 20170294337
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Application
    Filed: June 26, 2017
    Publication date: October 12, 2017
    Inventors: Jin-Nam KIM, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
  • Patent number: 9773699
    Abstract: In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: September 26, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Jin Lee, Rak-Hwan Kim, Byung-Hee Kim, Jin-Nam Kim, Tsukasa Matsuda, Wan-Soo Park, Nae-In Lee, Jae-Won Chang, Eun-Ji Jung, Jeong-Ok Cha, Jae-Won Hwang, Jung-Ha Hwang
  • Patent number: 9728604
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: August 8, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Nam Kim, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
  • Publication number: 20170133317
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film, a first trench having a first width, and a second trench having a second width, the second trench including an upper portion and a lower portion, the second width being greater than the first width, a first wire substantially filling the first trench and including a first metal, and a second wire substantially filling the second trench and including a lower wire and an upper wire, the lower wire substantially filling a lower portion of the second trench and including the first metal, and the upper wire substantially filling an upper portion of the second trench and including a second metal different from the first metal.
    Type: Application
    Filed: October 20, 2016
    Publication date: May 11, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Rak-Hwan KIM, Byung-Hee Kim, Jin-Nam Kim, Jong-Min Baek, Nae-In Lee, Eun-Ji Jung
  • Publication number: 20170072342
    Abstract: Disclosed is a pore adjusting filtering apparatus including: a cylinder having a plurality of holes and in which a screw is rotatably installed; an endless track coupled to an outer peripheral surface of the cylinder by a cylinder, an endless track pin, and a support to be rotatable together with the cylinder; a fiber yarn bundle support rod inserted into the endless track to be connected to the endless track; a fiber yarn bundle, one end of which is fitted with and supported by the fiber yarn bundle support rod; a fiber yarn bundle support net for supporting the fiber yarn bundle while being attached to an outer peripheral surface of the fiber yarn bundle; a cleaning separator fixedly installed at an upper outer side of the cylinder; and an ejector installed on an upper outer side of the cylinder.
    Type: Application
    Filed: November 4, 2016
    Publication date: March 16, 2017
    Applicants: Yoonjin Environment Co., Inc.
    Inventors: Jung-A RHIM, Jin-Gon YOON, Jeong-Hyo YOON, Je-Sung AHN, Jong-Won KIM, Jang-Gon IM, Hyen-Woo KIM, Eun-Joo SHIN, Sang-Hee KIM, Jeong-Hoon IM, Eun-Ji JUNG
  • Publication number: 20160300792
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Application
    Filed: March 3, 2016
    Publication date: October 13, 2016
    Inventors: Jin-Nam KIM, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
  • Publication number: 20160293484
    Abstract: In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.
    Type: Application
    Filed: January 19, 2016
    Publication date: October 6, 2016
    Inventors: Jong-Jin Lee, Rak-Hwan Kim, Byung-Hee Kim, Jin-Nam Kim, Tsukasa Matsuda, Wan-Soo Park, Nae-In Lee, Jae-Won Chang, Eun-Ji Jung, Jeong-Ok Cha, Jae-Won Hwang, Jung-Ha Hwang
  • Publication number: 20150209702
    Abstract: Disclosed is a pore adjusting filtering apparatus including: a cylinder having a plurality of holes and in which a screw is rotatably installed; an endless track coupled to an outer peripheral surface of the cylinder; a fiber yarn bundle support rod inserted into the endless track; a fiber yarn bundle fitted with and supported by the fiber yarn bundle support rod; a fiber yarn bundle support net for supporting the fiber yarn bundle; a cleaning separator fixedly installed at an upper outer side of the cylinder, for supporting the fiber yarn bundle support net; and an ejector installed on an upper outer side of the cylinder, for removing contaminants by ejecting water to the fiber yarn bundle while the fiber yarn bundle and the fiber yarn bundle support net are separated from each other.
    Type: Application
    Filed: April 8, 2014
    Publication date: July 30, 2015
    Applicants: Yoonjin Environment Co., Inc.
    Inventors: Jung-A RHIM, Jin-Gon YOON, Jeong-Hyo YOON, Je-Sung AHN, Jong-Won KIM, Jang-Gon IM, Hyen-Woo KIM, Eun-Joo SHIN, Sang-Hee KIM, Jeong-Hoon IM, Eun-Ji JUNG