Abstract: A method of manufacturing a semiconductor device includes: forming a trench for forming buried type wires by etching a substrate; forming first and second oxidation layers on a bottom of the trench and a wall of the trench, respectively; removing a part of the first oxidation layer and the entire second oxidation layer; and forming the buried type wires on the wall of the trench by performing a silicide process on the wall of the trench from which the second oxidation layer is removed. As a result, the buried type wires are insulated from each other.

Abstract: A microelectronic device includes a substrate including a via hole extending therethrough, a porous layer on sidewalls of the via hole, and a conductive via electrode extending through the via hole between the sidewalls thereof. The porous layer includes a plurality of pores therein that reduce a dielectric constant of the porous layer. Related fabrication methods are also discussed.

Abstract: A method of forming a buried gate electrode prevents voids from being formed in a silicide layer of the gate electrode. The method begins by forming a trench in a semiconductor substrate, forming a conformal gate oxide layer on the semiconductor in which the trench has been formed, forming a first gate electrode layer on the gate oxide layer, forming a silicon layer on the first gate electrode layer to fill the trench. Then, a portion of the first gate electrode layer is removed to form a recess which exposed a portion of a lateral surface of the silicon layer. A metal layer is then formed on the semiconductor substrate including on the silicon layer. Next, the semiconductor substrate is annealed while the lateral surface of the silicon layer is exposed to form a metal silicide layer on the silicon layer.

Abstract: A method of forming metal films includes preparing a substrate, on which an insulating layer and a metal layer formed of a first metal are exposed; and forming a metal capping layer by supplying an organic precursor of a second metal onto the substrate to deposit the second metal simultaneously on the insulating layer and the metal layer, wherein the second metal capping layer has different thicknesses on the insulating layer and the metal layer.

Abstract: A method of forming metal films includes preparing a substrate, on which an insulating layer and a metal layer formed of a first metal are exposed; and forming a metal capping layer by supplying an organic precursor of a second metal onto the substrate to deposit the second metal simultaneously on the insulating layer and the metal layer, wherein the second metal capping layer has different thicknesses on the insulating layer and the metal layer.

Abstract: A method of forming a gate electrode of a semiconductor device is provided, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a third silicon layer in an area from which the hard disk layer was removed, and forming a silicon layer comprising the third silicon layer and the second silicon layer; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the he first interlayer dielectric layer; and forming a metal silicide layer on the upper portion of the silicon layer.

Abstract: A method of manufacturing a non-volatile memory device including a tunnel oxide layer, a preliminary charge storing layer and a dielectric layer on a semiconductor layer is disclosed. A first polysilicon layer is formed on the dielectric layer. A barrier layer and a second polysilicon layer are formed on the first polysilicon layer. The second polysilicon layer, the barrier layer, the first polysilicon layer, the dielectric layer, the preliminary charge storing layer and the tunnel oxide layer are patterned to form a tunnel layer pattern, a charge storing layer pattern, a dielectric layer pattern, a first control gate pattern, a barrier layer pattern and a second polysilicon pattern. A nickel layer is formed on the second polysilicon layer. Heat treatment is performed with respect to the second polysilicon pattern and the nickel layer to form a second control gate pattern including NiSi on the barrier layer pattern.

Abstract: A method of fabricating a semiconductor device includes: forming a first polysilicon layer having a first thickness in a peripheral circuit region formed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region formed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; and forming gate electrodes by siliciding the first and second polysilicon layers.

Abstract: A method of forming a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate, and the interlayer insulating layer may have a contact hole therein exposing a portion of the semiconductor substrate. A single crystal semiconductor plug may be formed in the contact hole and on portions of the interlayer insulating layer adjacent the contact hole opposite the semiconductor substrate, and portions of the interlayer insulating layer opposite the semiconductor substrate may be free of the single crystal semiconductor plug. Portions of the single crystal semiconductor plug in the contact hole may be removed while maintaining portions of the single crystal semiconductor plug on portions of the interlayer insulating layer adjacent the contact hole as a single crystal semiconductor contact pattern.

Abstract: A plurality of spaced-apart conductor structures is formed on a semiconductor substrate, each of the conductor structures including a conductive layer. Insulating spacers are formed on sidewalls of the conductor structures. An interlayer-insulating film that fills gaps between adjacent ones of the insulating spacers is formed. Portions of the interlayer-insulating layer are removed to expose upper surfaces of the conductive layers. Respective epilayers are grown on the respective exposed upper surfaces of the conductive layers and respective metal silicide layers are formed from the respective epilayers.

Abstract: A method of forming an ohmic contact layer including forming an insulation layer pattern on a substrate, the insulation pattern layer having an opening selectively exposing a silicon bearing layer, forming a metal layer on the exposed silicon bearing layer using an electrode-less plating process, and forming a metal silicide layer from the silicon bearing layer and the metal layer using a silicidation process. Also, a method of forming metal wiring in a semiconductor device using the foregoing method of forming an ohmic contact layer.

Abstract: A semiconductor device includes a plurality of channel structures on a semiconductor substrate. A bit line groove having opposing sidewalls is defined between sidewalls of adjacent ones of the plurality of channel structures.

Abstract: There is provided a method of forming a semiconductor device having stacked transistors. When forming a contact hole for connecting the stacked transistors to each other, ohmic layers on the bottom and the sidewall of the common contact hole are separately formed. As a result, the respective ohmic layers are optimally formed to meet requirements or conditions. Accordingly, the contact resistance of the common contact may be minimized so that it is possible to enhance the speed of the semiconductor device.

Abstract: A method of manufacturing a semiconductor device includes: forming a trench for forming buried type wires by etching a substrate; forming first and second oxidation layers on a bottom of the trench and a wall of the trench, respectively; removing a part of the first oxidation layer and the entire second oxidation layer; and forming the buried type wires on the wall of the trench by performing a silicide process on the wall of the trench from which the second oxidation layer is removed. As a result, the buried type wires are insulated from each other.

Abstract: A method of forming a buried gate electrode prevents voids from being formed in a silicide layer of the gate electrode. The method begins by forming a trench in a semiconductor substrate, forming a conformal gate oxide layer on the semiconductor in which the trench has been formed, forming a first gate electrode layer on the gate oxide layer, forming a silicon layer on the first gate electrode layer to fill the trench. Then, a portion of the first gate electrode layer is removed to form a recess which exposed a portion of a lateral surface of the silicon layer. A metal layer is then formed on the semiconductor substrate including on the silicon layer. Next, the semiconductor substrate is annealed while the lateral surface of the silicon layer is exposed to form a metal silicide layer on the silicon layer.

Abstract: A semiconductor device includes a plurality of channel structures on a semiconductor substrate. A bit line groove having opposing sidewalls is defined between sidewalls of adjacent ones of the plurality of channel structures.

Abstract: A method of forming a buried interconnection includes removing a semiconductor substrate to form a groove in the semiconductor substrate. A metal layer is formed on inner walls of the groove using an electroless deposition technique. A silicidation process is applied to the substrate having the metal layer, thereby forming a metal silicide layer on the inner walls of the groove.

Abstract: A method of fabricating a semiconductor device includes: forming a first polysilicon layer having a first thickness in a peripheral circuit region formed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region formed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; and forming gate electrodes by siliciding the first and second polysilicon layers.

Abstract: A method of forming a gate electrode of a semiconductor device includes forming a first polysilicon layer in a peripheral circuit region of a substrate, forming a barrier layer on the first polysilicon layer, the barrier layer providing an ohmic contact, forming a stack structure including a tunneling insulation layer, an electric charge storing layer, and a blocking insulation layer in a memory cell region of the substrate, forming a second polysilicon layer on the barrier layer and the blocking insulation layer, and siliciding the second polysilicon layer and forming a silicide gate electrode.

Abstract: A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the lower interlevel insulation film over the upper transistor. The stacked semiconductor device further comprises a contact plug connected between a drain or source region of the lower transistor and a source or drain region of the upper transistor, and an extension layer connected to a lateral face of the source or drain region of the upper transistor to enlarge an area of contact between the source or drain region of the upper transistor and a side of the contact plug.