Abstract: A method of reading from a memory module which includes a plurality of memories is provided. The method includes reading data corresponding to a plurality of burst length units from the plurality of memories; correcting an error of the read data using a storage error correction code; and outputting the error corrected data by a unit of data corresponding to one burst length unit.

Abstract: An operating method is for a memory system which includes a NAND flash memory, a resistance variable memory, and a controller controlling the NAND flash memory and the resistance variable memory. The operating method includes receiving data, programming the received data in the NAND flash memory when the received data is at least a super page of data, programming the received data in the resistance variable memory when the received data is not a super page of data, and programming data accumulated in the resistance variable memory in the NAND flash memory when the accumulated data is a super page of data. A super page of data is an entirety of data that is programmable in memory cells connected to a same word line of the NAND flash memory.

Abstract: A nonvolatile memory is provided which includes a memory cell array including a plurality of nonvolatile memory cells; a decoder connected with the memory cell array through a plurality of word lines; a data input/output circuit connected with the memory cell array through a plurality of bit lines; a voltage detector configured to detect a variation in a power supply voltage to output a voltage variation signal; and control logic configured to control the decoder and the data input/output circuit such that data stored at the memory cell array is invalidated in response to the voltage variation signal.

Abstract: A memory system including a first memory of a first type; a second memory of a second type; and a controller configured to control the first memory and the second memory. The first type and second type are different, and the controller is configured to control the first memory and the second memory according to substantially the same command sequence.

Abstract: An error correcting method of a memory controller which controls a nonvolatile memory device includes judging whether first read data read from the nonvolatile memory device is correctable; reading second read data from the nonvolatile memory device when the first read data is uncorrectable; and correcting an error of the first read data based on error information of the second read data and error information of the first read data.

Abstract: A data storage device receives data and corresponding attribute data, stores the received data and the corresponding attribute data in a storage region of the data storage device, and automatically processes invalid data among the received data stored in the storage region based on the corresponding attribute data.

Abstract: A method of controlling a storage device comprises monitoring whether a quality of service (QoS) of the storage device satisfies a quality condition set through a host, and adjusting a current setting of at least one operation metric of the storage device related to the QoS, according to a result of the monitoring.

Abstract: A nonvolatile memory device comprises a memory cell array and a voltage generator. The memory cell array comprises a plurality of memory cells connected in series between a string selection transistor connected to a bit line and a ground selection transistor connected to a source line. The voltage generator provides read voltages to word lines of memory cells selected from among the plurality of memory cells during a read operation. The read voltages of the selected memory cells differ from each other according to their respective distances from the string selection transistor.

Abstract: A nonvolatile memory device comprises a memory cell array and a voltage generator. The memory cell array comprises a plurality of memory cells connected in series between a string selection transistor connected to a bit line and a ground selection transistor connected to a source line. The voltage generator provides read voltages to word lines of memory cells selected from among the plurality of memory cells during a read operation. The read voltages of the selected memory cells differ from each other according to their respective distances from the string selection transistor.

Abstract: A nonvolatile memory device comprises a memory cell array, a page buffer, and a bit line connection signal controller. The memory cell array comprises a plurality of word lines and bit lines arranged in rows and columns, and a plurality of memory cells connected to the respective word lines and bit lines. The page buffer connects a selected bit line among the plurality of bit lines to the page buffer, applies a precharge voltage to the selected bit line, and senses a voltage of the selected bit line after developing of the selected bit line according to a bit line connection signal, during a read operation. The bit line connection signal controller changes the bit line connection signal according to a control signal, during the read operation.

Abstract: A non-volatile memory may include a plurality of map blocks for storing a plurality of map units, the map units representing mapping information between physical addresses and logical addresses. A storage device may include such a non-volatile memory. A method of mapping such a non-volatile memory may include writing historical information regarding locations of valid map units among the map units included in map blocks previously allocated among the map blocks when a new map block among the map blocks is allocated, the valid map units representing valid mapping information, and constructing a map table including all of the valid mapping information based on the historical information and a result of searching a map block recently allocated among the map blocks.

Abstract: A method of reading from a memory module which includes a plurality of memories is provided. The method includes reading data corresponding to a plurality of burst length units from the plurality of memories; correcting an error of the read data using a storage error correction code; and outputting the error corrected data by a unit of data corresponding to one burst length unit.

Abstract: A nonvolatile memory is provided which includes a memory cell array including a plurality of nonvolatile memory cells; a decoder connected with the memory cell array through a plurality of word lines; a data input/output circuit connected with the memory cell array through a plurality of bit lines; a voltage detector configured to detect a variation in a power supply voltage to output a voltage variation signal; and control logic configured to control the decoder and the data input/output circuit such that data stored at the memory cell array is invalidated in response to the voltage variation signal.

Abstract: An operating method is for a memory system which includes a NAND flash memory, a resistance variable memory, and a controller controlling the NAND flash memory and the resistance variable memory. The operating method includes receiving data, programming the received data in the NAND flash memory when the received data is at least a super page of data, programming the received data in the resistance variable memory when the received data is not a super page of data, and programming data accumulated in the resistance variable memory in the NAND flash memory when the accumulated data is a super page of data. A super page of data is an entirety of data that is programmable in memory cells connected to a same word line of the NAND flash memory.

Abstract: A memory system including a first memory of a first type; a second memory of a second type; and a controller configured to control the first memory and the second memory. The first type and second type are different, and the controller is configured to control the first memory and the second memory according to substantially the same command sequence.

Abstract: Disclosed is an error correcting method of a memory controller which controls a nonvolatile memory device. The error correcting method includes judging whether first read data read from the nonvolatile memory device is correctable; reading second read data from the nonvolatile memory device when the first read data is uncorrectable; and correcting an error of the first read data based on error information of the second read data and error information of the first read data.

Abstract: A nonvolatile memory device comprises a memory cell array and a voltage generator. The memory cell array comprises a plurality of memory cells connected in series between a string selection transistor connected to a bit line and a ground selection transistor connected to a source line. The voltage generator provides read voltages to word lines of memory cells selected from among the plurality of memory cells during a read operation. The read voltages of the selected memory cells differ from each other according to their respective distances from the string selection transistor.

Abstract: A nonvolatile memory device comprises a memory cell array, a page buffer, and a bit line connection signal controller. The memory cell array comprises a plurality of word lines and bit lines arranged in rows and columns, and a plurality of memory cells connected to the respective word lines and bit lines. The page buffer connects a selected bit line among the plurality of bit lines to the page buffer, applies a precharge voltage to the selected bit line, and senses a voltage of the selected bit line after developing of the selected bit line according to a bit line connection signal, during a read operation. The bit line connection signal controller changes the bit line connection signal according to a control signal, during the read operation.

Abstract: A non-volatile memory may include a plurality of map blocks for storing a plurality of map units, the map units representing mapping information between physical addresses and logical addresses. A storage device may include such a non-volatile memory. A method of mapping such a non-volatile memory may include writing historical information regarding locations of valid map units among the map units included in map blocks previously allocated among the map blocks when a new map block among the map blocks is allocated, the valid map units representing valid mapping information, and constructing a map table including all of the valid mapping information based on the historical information and a result of searching a map block recently allocated among the map blocks.

Abstract: A memory card capable of having an increased number of meta blocks and a method of driving the memory card. A method of reading data from the memory card includes receiving logical addresses from a host. It is determined whether memory blocks corresponding to the received logical addresses belong to a first region allocated to a user data region in the memory card or a second region including meta blocks in the memory card. The memory blocks corresponding to the logical addresses are masked as erased blocks when the memory blocks belong to the second region.