Patents by Inventor Eun Jung Jo

Eun Jung Jo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10734324
    Abstract: A fan-out semiconductor package includes a core member having a first through-hole and including wiring layers; a first semiconductor chip disposed in the first through-hole and having first connection pads formed on a lower side of the first semiconductor chip; a first encapsulant covering the core member and the first semiconductor chip; a connection member disposed below the core member and the first semiconductor chip and including redistribution layers; a first stack chip disposed on the first encapsulant and electrically connected to the wiring layers through a first connection conductor; and a second encapsulant disposed on the first encapsulant and covering the first stack chip. The first semiconductor chip includes DRAM and/or a controller, the first stack chip includes a stack type NAND flash, and the first connection pads of the first semiconductor chip are electrically connected to the wiring layers through the redistribution layers.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: August 4, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yun Tae Lee, Eun Jung Jo, Han Kim
  • Patent number: 10676425
    Abstract: The present disclosure relates to an ?-aminoamide derivative compound and a pharmaceutical composition containing the same, for treating a neurodegenerative diseases.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: June 9, 2020
    Assignee: MEGABIOWOOD CO., LTD
    Inventors: Ki Duk Park, ChangJoon Justin Lee, Dong Jin Kim, Ae Nim Pae, Hyun Ah Choo, Sun Joon Min, Yong Koo Kang, Yun Kyung Kim, Hyo Jung Song, Ji Won Choi, Min Ho Nam, Jun Young Heo, Seul Ki Yeon, Bo Ko Jang, Eun Ji Ju, Seon Mi Jo, Jong-Hyun Park
  • Patent number: 10667419
    Abstract: There are provided an electronic component module in which an external terminal is disposed outwardly from a mold part by a plating process and a manufacturing method thereof. The electronic component module includes a substrate, at least one electronic component mounted on the substrate, a mold part sealing the electronic component, and at least one connection conductor having one end bonded to one surface of the substrate and formed in the mold part so as to penetrate through the mold part. The connection conductor is formed to have a form in which horizontal cross-sectional areas of the connection conductor are gradually reduced toward the substrate and includes at least one step.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: May 26, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Do Jae Yoo, Eun Jung Jo, Jae Hyun Lim
  • Patent number: 10642092
    Abstract: A polarizer including: a base layer including a first area and a second area enclosing the first area; a polarizing part disposed on the first area of the base layer and including a plurality of linear patterns spaced apart from each other; a dummy part disposed on the second area of the base layer and spaced apart from the polarizing part; and a hard mask residue part disposed on a portion of the second area of the base layer between the polarizing part and the dummy part and contacting the base layer. The polarizing part and the dummy part include a metal layer disposed on the base layer, and a hard mask layer disposed on the metal layer and comprising the same material as the hard mask residue part.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: May 5, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kang Soo Han, Eun Jung Kim, Gug Rae Jo
  • Patent number: 10580759
    Abstract: A fan-out semiconductor package includes a first core member including a first through-hole, a first semiconductor chip disposed in the first through-hole of the first core member, a first encapsulant configured to encapsulate at least a portion of the first semiconductor chip, a first connection member disposed on the first semiconductor chip and including a first redistribution layer, a second core member adhered to a lower surface of the first connection member and including a second through-hole, a second semiconductor chip disposed in the second through-hole of the second core member, a second encapsulant configured to encapsulate the second semiconductor chip, the second core member, and the first connection member, a second connection member disposed on the second semiconductor chip and including a second redistribution layer, and a connection via penetrating through the second core member and configured to electrically connect the first redistribution layer and the second redistribution layer.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: March 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun Jung Jo, Han Kim, Yoon Seok Seo
  • Patent number: 10483197
    Abstract: A semiconductor package includes a first connection member having a first surface and a second surface and including an insulating member and a first redistribution layer, a semiconductor chip connection electrodes disposed on the first connection member, an encapsulant on the second surface of the first connection member, including a photosensitive insulating material, and having a first region covering the active surface of the semiconductor chip and a second region in the vicinity of the semiconductor chip, a second redistribution layer including connection vias penetrating through the first region of the encapsulant, through-vias penetrating through the second region of the encapsulant, and a wiring pattern on the encapsulant and having an integrated structure with the connection vias and the through-vias, and a second connection member on the encapsulant including a third redistribution layer connected to the second redistribution layer.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: November 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun Jung Jo, Hyung Joon Kim, Han Kim, Bo Min Jeong
  • Publication number: 20190326223
    Abstract: A fan-out semiconductor package includes a core member having a first through-hole and including wiring layers; a first semiconductor chip disposed in the first through-hole and having first connection pads formed on a lower side of the first semiconductor chip; a first encapsulant covering the core member and the first semiconductor chip; a connection member disposed below the core member and the first semiconductor chip and including redistribution layers; a first stack chip disposed on the first encapsulant and electrically connected to the wiring layers through a first connection conductor; and a second encapsulant disposed on the first encapsulant and covering the first stack chip. The first semiconductor chip includes DRAM and/or a controller, the first stack chip includes a stack type NAND flash, and the first connection pads of the first semiconductor chip are electrically connected to the wiring layers through the redistribution layers.
    Type: Application
    Filed: October 25, 2018
    Publication date: October 24, 2019
    Inventors: Yun Tae LEE, Eun Jung JO, Han KIM
  • Publication number: 20190267351
    Abstract: A fan-out semiconductor package includes a first core member including a first through-hole, a first semiconductor chip disposed in the first through-hole of the first core member, a first encapsulant configured to encapsulate at least a portion of the first semiconductor chip, a first connection member disposed on the first semiconductor chip and including a first redistribution layer, a second core member adhered to a lower surface of the first connection member and including a second through-hole, a second semiconductor chip disposed in the second through-hole of the second core member, a second encapsulant configured to encapsulate the second semiconductor chip, the second core member, and the first connection member, a second connection member disposed on the second semiconductor chip and including a second redistribution layer, and a connection via penetrating through the second core member and configured to electrically connect the first redistribution layer and the second redistribution layer.
    Type: Application
    Filed: October 4, 2018
    Publication date: August 29, 2019
    Inventors: Eun Jung JO, Han KIM, Yoon Seok SEO
  • Publication number: 20190189549
    Abstract: A semiconductor package includes a first connection member having a first surface and a second surface and including an insulating member and a first redistribution layer, a semiconductor chip connection electrodes disposed on the first connection member, an encapsulant on the second surface of the first connection member, including a photosensitive insulating material, and having a first region covering the active surface of the semiconductor chip and a second region in the vicinity of the semiconductor chip, a second redistribution layer including connection vias penetrating through the first region of the encapsulant, through-vias penetrating through the second region of the encapsulant, and a wiring pattern on the encapsulant and having an integrated structure with the connection vias and the through-vias, and a second connection member on the encapsulant including a third redistribution layer connected to the second redistribution layer.
    Type: Application
    Filed: April 25, 2018
    Publication date: June 20, 2019
    Inventors: Eun Jung Jo, Hyung Joon Kim, Han Kim, Bo Min Jeong
  • Publication number: 20190189600
    Abstract: The fan-out semiconductor package includes: a metal member including a metal plate having a first through-hole and second through-holes and metal posts disposed in the second through-holes; a semiconductor chip disposed in the first through-hole; an encapsulant covering at least portion of each of the metal member and the semiconductor chip and filling at least portions of each of the first and second through-holes; a wiring layer disposed on the encapsulant; first vias electrically connecting the wiring layer and the connection pads to each other; and second vias electrically connecting the wiring layer and the metal posts to each other, wherein a height of the second vias is greater than that of the first vias or a thickness of the metal plate is the same as that of the metal post.
    Type: Application
    Filed: April 25, 2018
    Publication date: June 20, 2019
    Inventors: Jae Hyun LIM, Han KIM, Eun Jung JO, Jung Ho SHIM, Sang Jong LEE, Hyung Joon KIM
  • Patent number: 10325891
    Abstract: The fan-out semiconductor package includes: a metal member including a metal plate having a first through-hole and second through-holes and metal posts disposed in the second through-holes; a semiconductor chip disposed in the first through-hole; an encapsulant covering at least portion of each of the metal member and the semiconductor chip and filling at least portions of each of the first and second through-holes; a wiring layer disposed on the encapsulant; first vias electrically connecting the wiring layer and the connection pads to each other; and second vias electrically connecting the wiring layer and the metal posts to each other, wherein a height of the second vias is greater than that of the first vias or a thickness of the metal plate is the same as that of the metal post.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: June 18, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jae Hyun Lim, Han Kim, Eun Jung Jo, Jung Ho Shim, Sang Jong Lee, Hyung Joon Kim
  • Publication number: 20190164893
    Abstract: A semiconductor package includes: an interposer having a first surface and a second surface and including a first redistribution layer; a semiconductor chip having an active surface having connection electrodes disposed thereon and an inactive surface and disposed on the interposer so that the inactive surface faces the second surface of the interposer; an encapsulant disposed on the second surface of the interposer, including a photosensitive insulating material, and having a first region covering the semiconductor chip and a second region positioned around the semiconductor chip; and a second redistribution layer including second vias penetrating through the first region of the encapsulant and connected to the connection electrodes, through-vias penetrating through the second region of the encapsulant and connected to the first redistribution layer, and second wiring patterns disposed on the encapsulant and having integrated structures with the second vias and the through-vias.
    Type: Application
    Filed: March 29, 2018
    Publication date: May 30, 2019
    Inventors: Han KIM, Eun Jung JO, Jung Ho SHIM
  • Publication number: 20190162891
    Abstract: A polarizer includes a buffer member and linear metal patterns. The buffer member includes protrusions. Each protrusion has downwardly-increasing width. The buffer member is formed of polymer. The linear metal patterns, spaced apart from each other, are extended in a first direction. Each linear metal pattern covers a respective protrusion.
    Type: Application
    Filed: January 30, 2019
    Publication date: May 30, 2019
    Inventors: Kang-Soo Han, Eun-Jung Kim, Gug-Rae Jo, Hyung-Bin Cho
  • Patent number: 10304807
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a first encapsulant encapsulating at least portions of the first interconnection member and the first semiconductor chip; a second interconnection member disposed on the first interconnection member and the first semiconductor chip; a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; and a second encapsulant encapsulating at least portions of the second semiconductor chip.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dae Hyun Park, Eun Jung Jo, Sung Won Jeong, Han Kim, Mi Ja Han
  • Patent number: 10157886
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a first encapsulant encapsulating at least portions of the first interconnection member and the first semiconductor chip; a second interconnection member disposed on the first interconnection member and the first semiconductor chip; a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; and a second encapsulant encapsulating at least portions of the second semiconductor chip.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: December 18, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dae Hyun Park, Eun Jung Jo, Sung Won Jeong, Han Kim, Mi Ja Han
  • Patent number: 10121769
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a first encapsulant encapsulating at least portions of the first interconnection member and the first semiconductor chip; a second interconnection member disposed on the first interconnection member and the first semiconductor chip; a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; and a second encapsulant encapsulating at least portions of the second semiconductor chip.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: November 6, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dae Hyun Park, Eun Jung Jo, Sung Won Jeong, Han Kim, Mi Ja Han
  • Patent number: 10096552
    Abstract: A fan-out semiconductor package includes: a first semiconductor chip; a first encapsulant; a connection member including first vias and a first redistribution layer; a second semiconductor chip; a second encapsulant; a second redistribution layer; second vias; and third vias. A length of the longest side of a first cut surface of the second via is less than that of the longest side of a second cut surface of the third via, the first cut surface of the second via and the second cut surface of the third via being cut by a plane on any level parallel to the second active surface.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: October 9, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Han Kim, Eun Jung Jo, Jung Ho Shim
  • Publication number: 20180233489
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a first encapsulant encapsulating at least portions of the first interconnection member and the first semiconductor chip; a second interconnection member disposed on the first interconnection member and the first semiconductor chip; a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; and a second encapsulant encapsulating at least portions of the second semiconductor chip.
    Type: Application
    Filed: April 12, 2018
    Publication date: August 16, 2018
    Inventors: Dae Hyun PARK, Eun Jung JO, Sung Won JEONG, Han KIM, Mi Ja HAN
  • Publication number: 20180190591
    Abstract: A fan-out semiconductor package includes: a first semiconductor chip; a first encapsulant; a connection member including first vias and a first redistribution layer; a second semiconductor chip; a second encapsulant; a second redistribution layer; second vias; and third vias. A length of the longest side of a first cut surface of the second via is less than that of the longest side of a second cut surface of the third via, the first cut surface of the second via and the second cut surface of the third via being cut by a plane on any level parallel to the second active surface.
    Type: Application
    Filed: August 29, 2017
    Publication date: July 5, 2018
    Inventors: Han KIM, Eun Jung JO, Jung Ho SHIM
  • Patent number: 9995741
    Abstract: The present disclosure relates to a complex for detecting a target material comprising upconverting nanoparticles; and at least one target material specific aptamer-quencher, connected through a linker with the upconverting nanoparticles, a method of preparing the same, a kit for detecting a target material comprising the same, and a method of detecting a target material using the same. According to the present disclosure, different target materials in samples can be quantified or detected accurately based on luminescence resonance energy transfer (LRET) of the upconverting nanoparticles (UCNPs) excited by a near infrared (NIR) light source.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: June 12, 2018
    Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Min-Gon Kim, Eun-Jung Jo, Hyo-Young Mun