Abstract: In a method of manufacturing a semiconductor device, a preliminary active pattern including gate layers and channel layers is formed on a substrate. The gate layers and the channel layers are alternatively stacked. A hard mask is formed on the preliminary active pattern. The preliminary active pattern is partially etched using the hard mask as an etching mask to expose a surface of the substrate. The etched preliminary active pattern is trimmed to form an active channel pattern having a width less than a lower width of the hard mask. Source/drain layers are formed on exposed side faces of the active channel pattern and the surface. The gate layers are selectively etched to form tunnels. A gate encloses the active channel pattern and filling the tunnels. Related intermediate structures are also disclosed.

Abstract: Electromechanical non-volatile memory devices are provided including a semiconductor substrate having an upper surface including insulation characteristics. A first electrode pattern is provided on the semiconductor substrate. The first electrode pattern exposes portions of a surface of the semiconductor substrate therethrough. A conformal bit line is provided on the first electrode pattern and the exposed surface of semiconductor substrate. The bit line is spaced apart from a sidewall of the first electrode pattern and includes a conductive material having an elasticity generated by a voltage difference. An insulating layer pattern is provided on an upper surface of the bit line located on the semiconductor substrate. A second electrode pattern is spaced apart from the bit line and provided on the insulating layer pattern. The second electrode pattern faces the first electrode pattern.

Abstract: A non-volatile memory device, and method of forming the same, increases or maximizes the performance of an ultramicro-structured device.

Abstract: A memory device includes a first active region on a substrate and first and second source/drain regions on the substrate abutting respective first and second sidewalls of the first active region. A first gate structure is disposed on the first active region between the first and second source/drain regions. A second active region is disposed on the first gate structure between and abutting the first and second source/drain regions. A second gate structure is disposed on the second active region overlying the first gate structure.

Abstract: In a method of forming a pattern, a sacrificial layer pattern and a stop layer pattern for preventing or reducing an epitaxial growth may be formed on a substrate. The sacrificial layer pattern may have a first hole therethrough, and the first hole partially exposes a top surface of the substrate. At least one active pattern may be formed on a bottom and a sidewall of the first hole by performing a selective epitaxial growth process on the top surface of the substrate and a sidewall of the sacrificial layer pattern. The sacrificial layer pattern and the stop layer pattern for preventing or reducing the epitaxial growth may be removed from the substrate. The at least one active pattern formed by the above method may have a finer size and an improved shaped compared to a conventional active pattern formed by directly patterning layers using a photoresist pattern. Damages in a photolithography process may be prevented or reduced from being generated.

Abstract: A semiconductor memory device includes a substrate having first and second source/drain regions therein and a channel region therebetween. The device also includes first and second charge storage layers on the channel region, a first insulating layer on the channel region between the first and second charge storage layers, and a gate electrode on the insulating layer opposite the channel region and between inner sidewalls of the first and second charge storage layers. The gate electrode extends away from the substrate beyond the first and second charge storage layers. The device further includes second and third insulating layers extending from adjacent the inner sidewalls of the first and second charge storage layers along portions of the gate electrode beyond the first and second charge storage layers. Related methods of fabrication are also discussed.

Abstract: A semiconductor device having a field effect transistor and a method of fabricating the same. In-situ doped epitaxial patterns are respectively formed at both sidewalls of a protruded channel pattern from a substrate by performing an in-situ doped epitaxial growth process. The in-situ doped epitaxial pattern has a conformal impurity concentration throughout. Accordingly, source/drain regions with a conformal impurity concentration are connected throughout a channel width of a channel region including both sidewalls of a protruded channel pattern. As a result, it is possible to maximize a driving current of the filed effect transistor, and an on-off characteristic can be highly stabilized.

Abstract: A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between the overlaid source/drain regions of the respective first and second pairs of overlaid source/drain regions and adjacent respective ones of the first and second vertical channel regions. Respective first and second gate insulators are disposed on respective ones of the first and second vertical channel regions. A gate electrode is disposed between the first and second gate insulators. The first and second vertical channel regions may be disposed near adjacent edges of the overlaid source/drain regions.

Abstract: In a method of manufacturing a semiconductor device, a preliminary active pattern including gate layers and channel layers is formed on a substrate. The gate layers and the channel layers are alternatively stacked. A hard mask is formed on the preliminary active pattern. The preliminary active pattern is partially etched using the hard mask as an etching mask to expose a surface of the substrate. The etched preliminary active pattern is trimmed to form an active channel pattern having a width less than a lower width of the hard mask. Source/drain layers are formed on exposed side faces of the active channel pattern and the surface. The gate layers are selectively etched to form tunnels. A gate encloses the active channel pattern and filling the tunnels. Related intermediate structures are also disclosed.

Abstract: Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.

Abstract: Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.

Abstract: In a method of fabricating a fin field effect transistor having a plurality of protruding channels, the fin field effect transistor is formed by forming a dummy gate pattern on a first hard mask pattern and a first insulating layer on a semiconductor substrate having an active region pattern, forming a source and drain region in a portion of the active region pattern, forming a plurality of vertically protruding channels between the source and drain region, forming a gate dielectric layer on the active region pattern having the plurality of protruding channels, and forming a gate electrode on the gate dielectric layer.

Abstract: A semiconductor device having a field effect transistor and a method of fabricating the same. In-situ doped epitaxial patterns are respectively formed at both sidewalls of a protruded channel pattern from a substrate by performing an in-situ doped epitaxial growth process. The in-situ doped epitaxial pattern has a conformal impurity concentration throughout. Accordingly, source/drain regions with a conformal impurity concentration are connected throughout a channel width of a channel region including both sidewalls of a protruded channel pattern. As a result, it is possible to maximize a driving current of the filed effect transistor, and an on-off characteristic can be highly stabilized.

Abstract: A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mono-crystalline silicon substrate, etching the substrate to form a pair of spaced-apart trenches such that a wall of the mono-crystalline silicon stands between the trenches, filling the trenches with insulative material, implanting impurities into the wall of mono-crystalline silicon, and forming an opening in the wall such that portions of the wall remain as pillars. A sacrificial layer is formed at the bottom of the opening. Then, the channel region is formed atop the sacrificial layer between the pillars. The sacrificial layer is subsequently removed and the gate oxide and gate electrode are formed around the channel region.

Abstract: A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mono-crystalline silicon substrate, etching the substrate to form a pair of spaced-apart trenches such that a wall of the mono-crystalline silicon stands between the trenches, filling the trenches with insulative material, implanting impurities into the wall of mono-crystalline silicon, and forming an opening in the wall such that portions of the wall remain as pillars. A sacrificial layer is formed at the bottom of the opening. Then, the channel region is formed atop the sacrificial layer between the pillars. The sacrificial layer is subsequently removed and the gate oxide and gate electrode are formed around the channel region.

Abstract: In a semiconductor device having a multi-bridge-channel, and a method for fabricating the same, the device includes first and second semiconductor posts protruding from a surface of a semiconductor substrate and having a source and a drain region, respectively, in upper side portions thereof, channel semiconductor layers connecting upper side portions of the first and second semiconductor posts, a gate insulation layer on the channel semiconductor layers and the semiconductor substrate, the gate insulation layer surrounding at least a portion of the channel semiconductor layers, a gate electrode layer on the gate insulation layer to enclose at least a portion of a region between the channel semiconductor layers, and junction auxiliary layers formed between the channel semiconductor layers, the junction auxiliary layers contacting the gate electrode layer and upper side portions of the first and second semiconductor posts, and having a same width as the channel semiconductor layers.

Abstract: In one embodiment, a method of fabricating a semiconductor device having a crystalline semiconductor layer includes preparing a semiconductor substrate and forming a preliminary active pattern on the semiconductor substrate. The preliminary active pattern includes a barrier pattern and a non-single crystal semiconductor pattern. A sacrificial non-single crystal semiconductor layer covers the preliminary active pattern and the semiconductor substrate. By crystallizing the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern, using the semiconductor substrate as a seed layer, the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern are changed to a sacrificial crystalline semiconductor layer and a crystalline semiconductor pattern, respectively. The crystalline semiconductor pattern and the barrier pattern constitute an active pattern. The sacrificial crystalline semiconductor layer is removed.

Abstract: A Schottky barrier FinFET device and a method of fabricating the same are provided. The device includes a lower fin body provided on a substrate. An upper fin body having first and second sidewalls which extend upwardly from a center of the lower fin body and face each other is provided. A gate structure crossing over the upper fin body and covering an upper surface of the upper fin body and the first and second sidewalls is provided. The Schottky barrier FinFET device includes a source and a drain which are formed on the sidewalls of the upper fin body adjacent to sidewalls of the gate structure and made of a metal material layer formed on an upper surface of the lower fin body positioned at both sides of the upper fin body, and the source and drain form a Schottky barrier to the lower and upper fin bodies.

Abstract: A method of fabricating a semiconductor device includes sequentially forming a first pattern and a second pattern on a substrate, the second pattern being a non-single-crystalline semiconductor stacked on the first pattern, wherein a portion of the substrate is exposed adjacent to the first and second patterns, forming a non-single-crystalline semiconductor layer on the substrate, the semiconductor layer contacting the second pattern and the exposed portion of the substrate, and, using the substrate as a seed layer, changing the crystalline state of the semiconductor layer to be single-crystalline and changing the crystalline state of the second pattern to be single-crystalline.

Abstract: In a semiconductor device having a multi-bridge-channel, and a method for fabricating the same, the device includes first and second semiconductor posts protruding from a surface of a semiconductor substrate and having a source and a drain region, respectively, in upper side portions thereof, channel semiconductor layers connecting upper side portions of the first and second semiconductor posts, a gate insulation layer on the channel semiconductor layers and the semiconductor substrate, the gate insulation layer surrounding at least a portion of the channel semiconductor layers, a gate electrode layer on the gate insulation layer to enclose at least a portion of a region between the channel semiconductor layers, and junction auxiliary layers formed between the channel semiconductor layers, the junction auxiliary layers contacting the gate electrode layer and upper side portions of the first and second semiconductor posts, and having a same width as the channel semiconductor layers.