Abstract: Gate-all-around integrated circuit devices include first and second source/drain regions on an active area of an integrated circuit substrate. The first and second source/drain regions form p-n rectifying junctions with the active area. A channel region extends between the first and second source/drain regions. An insulated gate electrode surrounds the channel region.

Abstract: A method of manufacturing a MOS transistor with a multiple channel structure prevents damage to and loss of material of a channel region. The method includes: forming a stacked structure including a plurality of first material layers and a plurality of second material layers that have different etching selectivities and are alternately stacked on a semiconductor substrate; forming an active mask on a portion of the stacked structure, the active mask defining an active region; etching regions of the stacked structure to expose sidewalls of the stacked structure; forming a plurality of tunnels by selectively removing the first material layer between the exposed sidewalls of the stacked structure; removing the active mask; and forming a gate electrode on the active region to fill the plurality of tunnels.

Abstract: Some embodiments of the present invention provide methods and apparatus for operating a transistor including at least one fully depleted channel region in and/or on a substrate. The methods include applying a reverse body bias to the substrate when turning on the transistor. The substrate may be a bulk wafer substrate. The reverse body bias may allow the transistor to turn on while preventing turn on of a parasitic transistor in the substrate.

Abstract: A unit cell of a metal oxide semiconductor (MOS) transistor is provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. First and second spaced apart buffer regions are provided beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.

Abstract: A field effect transistor on an active region of a semiconductor substrate includes a vertically protruding thin-body portion of the semiconductor substrate and a vertically oriented gate electrode at least partially inside a cavity defined by opposing sidewalls of the vertically protruding portion of the substrate. The transistor further includes an insulating layer surrounding an upper portion of the vertically oriented gate electrode and a laterally oriented gate electrode on the insulating layer and connected to a top portion of the vertically oriented gate electrode. Accordingly, a T-shaped gate electrode is defined having a lateral portion on a top surface of a semiconductor substrate and having a vertical portion at least partially inside a cavity defined by opposing sidewalls of a vertically protruding portion of the substrate.

Abstract: Provided are a multi-channel semiconductor device and a method for manufacturing the semiconductor device through a simplified process. A sacrificial layer and a channel layer are alternately stacked on a semiconductor substrate. Thereafter, the sacrificial layer and the channel layer are etched to form a separated active pattern, and a device isolation layer is formed to cover sidewalls of the active pattern. Dopant ions are implanted into the entire semiconductor substrate, thereby forming a channel separation region under the active pattern. A portion of the active pattern is etched to separate the active pattern from a pair of facing sidewalls of the device separation layer, thereby forming a channel pattern having a pair of first exposed sidewalls. Source/drain semiconductor layers are formed on the first sidewalls of the channel pattern, and a part of the device isolation layer is removed to expose a pair of second sidewalls of the channel pattern contacting with the device separation layer.

Abstract: A FinFET semiconductor device has an active region formed of a semiconductor substrate and projecting from a surface of the substrate. A fin having a first projection and a second projection composed of the active region are arranged in parallel and at each side of a central trench formed in a central portion of the active region. Upper surfaces and side surfaces of the first projection and the second projection comprise a channel region. A channel ion implantation layer is provided at a bottom of the central trench and at a lower portion of the fin. A gate oxide layer is provided on the fin. A gate electrode is provided on the gate oxide layer. A source region and a drain region are provided in the active region at sides of the gate electrode.

Abstract: Methods of forming a unit cell of a metal oxide semiconductor (MOS) transistor are provided. An integrated circuit substrate is formed. A MOS transistor is formed on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. The first and second spaced apart buffer regions are formed beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.

Abstract: In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device.

Abstract: In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on both sides of the channel region in the silicon layer. Integration can be improved by storing data in a 3-dimensional manner; a 2-bit operation can be performed by providing transistors on both sides of the gate.

Abstract: Provided are a semiconductor device including a FinFET having a metal gate electrode and a fabricating method thereof. The semiconductor device includes: an active area formed in a semiconductor substrate and protruding from a surface of the semiconductor substrate; a fin including first and second protrusions formed of a surface of the active area and parallel with each other based on a central trench formed in the active area and using upper surfaces and sides of the first and second protrusions as a channel area; a gate insulating layer formed on the active area including the fin; a metal gate electrode formed on the gate insulating layer; a gate spacer formed on a sidewall of the metal gate electrode; and a source and a drain formed in the active area beside both sides of the metal gate electrode. Here, the metal gate electrode comprises a barrier layer contacting the gate spacer and the gate insulating layer and a metal layer formed on the barrier layer.

Abstract: In a method of fabricating a fin field effect transistor having a plurality of protruding channels, the fin field effect transistor is formed by forming a dummy gate pattern on a first hard mask pattern and a first insulating layer on a semiconductor substrate having an active region pattern, forming a source and drain region in a portion of the active region pattern, forming a plurality of vertically protruding channels between the source and drain region, forming a gate dielectric layer on the active region pattern having the plurality of protruding channels, and forming a gate electrode on the gate dielectric layer.

Abstract: Multi-bit nonvolatile memory devices and related methods of manufacturing the same are described. In some multi-bit nonvolatile memory devices, a semiconductor substrate has a recessed region defined therein. An insulating layer, which can include an ONO layer, is configured to store data within programming regions therein, and covers a sidewall and a lower surface of the recess region. A gate electrode is on the insulating layer in the recessed region. At least one pair of impurity regions are in the semiconductor substrate. The impurity regions adjoin a side surface of the insulating layer in the recess region and form a relative angle that is less than 120° therebetween with respect to a center of the gate electrode.

Abstract: A complementary metal-oxide semiconductor (CMOS) device includes an NMOS thin body channel including a silicon epitaxial layer. An NMOS insulating layer is formed on a surface of the NMOS thin body channel and surrounds the NMOS thin body channel. An NMOS metal gate is formed on the NMOS insulating layer. The CMOS device further includes a p-channel metal-oxide semiconductor (PMOS) transistor including a PMOS thin body channel including a silicon epitaxial layer. A PMOS insulating layer is formed on a surface of and surrounds the PMOS thin body channel. A PMOS metal gate is formed on the PMOS insulating layer. The NMOS insulating layer includes a silicon oxide layer and the PMOS insulating layer includes an electron-trapping layer, the NMOS insulating layer includes a hole trapping dielectric layer and the PMOS insulating layer includes a silicon oxide layer, or the NMOS insulating layer includes a hole-trapping dielectric layer and the PMOS insulating layer includes an electron-trapping dielectric layer.

Abstract: In a semiconductor device having a multi-bridge-channel, and a method for fabricating the same, the device includes first and second semiconductor posts protruding from a surface of a semiconductor substrate and having a source and a drain region, respectively, in upper side portions thereof, channel semiconductor layers connecting upper side portions of the first and second semiconductor posts, a gate insulation layer on the channel semiconductor layers and the semiconductor substrate, the gate insulation layer surrounding at least a portion of the channel semiconductor layers, a gate electrode layer on the gate insulation layer to enclose at least a portion of a region between the channel semiconductor layers, and junction auxiliary layers formed between the channel semiconductor layers, the junction auxiliary layers contacting the gate electrode layer and upper side portions of the first and second semiconductor posts, and having a same width as the channel semiconductor layers.

Abstract: In a semiconductor memory device and method, phase-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices formed of a phase-change material. Each phase-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of phase-change memory cell groups storing data while being connected to the local bit lines, respectively.

Abstract: A semiconductor memory device includes a substrate having first and second source/drain regions therein and a channel region therebetween. The device also includes first and second charge storage layers on the channel region, a first insulating layer on the channel region between the first and second charge storage layers, and a gate electrode on the insulating layer opposite the channel region and between inner sidewalls of the first and second charge storage layers. The gate electrode extends away from the substrate beyond the first and second charge storage layers. The device further includes second and third insulating layers extending from adjacent the inner sidewalls of the first and second charge storage layers along portions of the gate electrode beyond the first and second charge storage layers. Related methods of fabrication are also discussed.

Abstract: An integrated circuit device structure can be formed by forming an implant mask having a window therein on a structure including upper and lower Si layers and an intermediate SiGex layer therebetween. Ions are implanted through the upper Si layer and into a portion of the intermediate SiGex layer exposed through the window in the implant mask and blocking implantation of ions into portions of the intermediate SiGex layer outside the window. The portions of the intermediate SiGex layer outside the window are etched and the portion of the intermediate SiGex layer exposed through the window having ions implanted therein is not substantially etched to form a patterned intermediate SiGex layer.

Abstract: A multi-bridge-channel MOSFET (MBCFET) may be formed by forming a stacked structure on a substrate that includes channel layers and interchannel layers interposed between the channel layers. Trenches are formed by selectively etching the stacked structure. The trenches run across the stacked structure parallel to each other and separate a first stacked portion including channel patterns and interchannel patterns from second stacked portions including channel and interchannel layers remaining on both sides of the first stacked portion. First source and drain regions are grown using selective epitaxial growth. The first source and drain regions fill the trenches and connect to second source and drain regions defined by the second stacked portions. Marginal sections of the interchannel patterns of the first stacked portion are selectively exposed. Through tunnels are formed by selectively removing the interchannel patterns of the first stacked portion beginning with the exposed marginal sections.

Abstract: A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mono-crystalline silicon substrate, etching the substrate to form a pair of spaced-apart trenches such that a wall of the mono-crystalline silicon stands between the trenches, filling the trenches with insulative material, implanting impurities into the wall of mono-crystalline silicon, and forming an opening in the wall such that portions of the wall remain as pillars. A sacrificial layer is formed at the bottom of the opening. Then, the channel region is formed atop the sacrificial layer between the pillars. The sacrificial layer is subsequently removed and the gate oxide and gate electrode are formed around the channel region.