Abstract: Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer.

Abstract: Provided is a method of fabricating a semiconductor microstructure, the method including forming a lower material layer on a semiconductor substrate, the lower material layer including a nitride of a Group III-element; forming a mold material layer on the lower material layer; forming an etching mask on the mold material layer, the etching mask being for forming a structure in the mold material layer; anisotropic-etching the mold material layer and the lower material layer by using the etching mask; and isotropic-etching the mold material layer and the lower material layer.

Abstract: In some embodiments, a semiconductor substrate includes trenches defining active regions. The semiconductor device further includes lower and upper device isolation patterns disposed in the trenches. An intergate insulation pattern and a control gate electrode are disposed on the semiconductor substrate to cross over the active regions. A charge storage electrode is between the control gate electrode and the active regions. A gate insulation pattern is between the charge storage electrode and the active regions, and the intergate insulation pattern directly contacts the upper device isolation pattern between the active regions.

Abstract: Provided is a method of fabricating a semiconductor microstructure, the method including forming a lower material layer on a semiconductor substrate, the lower material layer including a nitride of a Group III-element; forming a mold material layer on the lower material layer; forming an etching mask on the mold material layer, the etching mask being for forming a structure in the mold material layer; anisotropic-etching the mold material layer and the lower material layer by using the etching mask; and isotropic-etching the mold material layer and the lower material layer.

Abstract: A method of fabricating a semiconductor device includes forming a lower device on a lower semiconductor substrate, and forming an interlayer insulating film on the lower device. An upper semiconductor substrate is formed on the interlayer insulating film such that the interlayer insulating film is between the lower and upper semiconductor substrates. Upper trenches are formed within the upper semiconductor substrate. An upper device isolating film is formed within the upper trenches. The upper device isolating film is irradiated with ultraviolet light having a wavelength configured to break chemical bonds of impurities in the upper device isolating film to reduce an impurity concentration thereof.

Abstract: A method of filling a trench in a substrate ensures that a void or seam is not left in the material occupying the trench. First, a preliminary insulating layer is formed so as to extend contiguously along the bottom and sides of the trench and along an upper surface of the substrate. Impurities are then implanted into a portion of the preliminary insulating layer adjacent the top of the first trench to form a first insulating layer having a doped region and an undoped region. The doped region is removed to form a first insulating layer pattern at the bottom and sides of the first trench, and which first insulating layer pattern defines a second trench. The second trench is then filled with insulating material.

Abstract: One embodiment of a method of fabricating a flash memory device includes forming a trench mask pattern, which includes a gate insulation pattern and a charge storage pattern stacked in sequence, on a semiconductor substrate; etching the semiconductor substrate using the trench mask pattern as an etch mask to form trenches defining active regions; and sequentially forming lower and upper device isolation patterns in the trench. After sequentially forming an intergate insulation film and a control gate film on the upper device isolation pattern, the control gate film, the intergate insulation pattern and the gloating gate pattern are formed, thereby providing gate lines crossing over the active regions.

Abstract: A semiconductor device having a trench isolation region and methods of fabricating the same are provided. The method includes forming a first trench region in a substrate, and a second trench region having a larger width than the first trench region in the substrate. A lower material layer may fill the first and second trench regions. The lower material layer may be etched by a first etching process to form a first preliminary lower material layer pattern remaining in the first trench region and form a second preliminary lower material layer pattern that remains in the second trench region. An upper surface of the second preliminary lower material layer pattern may be at a different height than the first preliminary lower material layer pattern. The first and second preliminary lower material layer patterns may be etched by a second etching process to form first and second lower material layer patterns having top surfaces at substantially the same height.

Abstract: Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer.

Abstract: In a method of forming an isolation layer, a plurality of trenches is formed on a substrate. A liner is formed on inner walls of the trenches. The liner is thermally oxidized to fill up some of the trenches. The other trenches are filled up with an insulation material. As a result, the isolation layer is free of voids.

Abstract: Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill recessed trench regions formed in the substrate. The first oxide layer and the SOG layer are then subjected to a planarization sequence including a CMP process followed by an etchback process to form a composite structure having a substantially flat upper surface that exposes both the oxide and the SOG material. The second oxide layer is then applied and subjected to a similar CMP/etchback sequence to obtain a composite structure having an upper surface that is recessed relative to a plane defined by the surfaces of adjacent active regions.

Abstract: A method of filling a trench in a substrate ensures that a void or seam is not left in the material occupying the trench. First, a preliminary insulating layer is formed so as to extend contiguously along the bottom and sides of the trench and along an upper surface of the substrate. Impurities are then implanted into a portion of the preliminary insulating layer adjacent the top of the first trench to form a first insulating layer having a doped region and an undoped region. The doped region is removed to form a first insulating layer pattern at the bottom and sides of the first trench, and which first insulating layer pattern defines a second trench. The second trench is then filled with insulating material.

Abstract: A semiconductor device may include a semiconductor substrate, trench region, buffer pattern, gap fill layer, and transistor. The trench region may be provided in the semiconductor substrate to define an active region. The buffer pattern and gap fill layer may be provided in the trench region. The buffer pattern and gap fill layer may fill the trench region. The gap fill layer may be densified by the buffer pattern. The transistor may be provided in the active region. A method of manufacturing a semiconductor device may include: forming a trench region in a semiconductor substrate; forming a buffer layer on an inner wall of the first trench region; forming a gap fill layer, filling the trench region; performing a thermal process to react the impurity with the oxygen, forming a buffer pattern; and forming a transistor in the active region.

Abstract: A semiconductor device having a trench isolation region and methods of fabricating the same are provided. The method includes forming a first trench region in a substrate, and a second trench region having a larger width than the first trench region in the substrate. A lower material layer may fill the first and second trench regions. The lower material layer may be etched by a first etching process to form a first preliminary lower material layer pattern remaining in the first trench region and form a second preliminary lower material layer pattern that remains in the second trench region. An upper surface of the second preliminary lower material layer pattern may be at a different height than the first preliminary lower material layer pattern. The first and second preliminary lower material layer patterns may be etched by a second etching process to form first and second lower material layer patterns having top surfaces at substantially the same height.

Abstract: A method of fabricating a semiconductor device includes forming a lower device on a lower semiconductor substrate, and forming an interlayer insulating film on the lower device. An upper semiconductor substrate is formed on the interlayer insulating film such that the interlayer insulating film is between the lower and upper semiconductor substrates. Upper trenches are formed within the upper semiconductor substrate. An upper device isolating film is formed within the upper trenches. The upper device isolating film is irradiated with ultraviolet light having a wavelength configured to break chemical bonds of impurities in the upper device isolating film to reduce an impurity concentration thereof.

Abstract: A method of forming a hydrocarbon-containing polymer film on a semiconductor substrate by a capacitively-coupled plasma CVD apparatus. The method includes the steps of: vaporizing a hydrocarbon-containing liquid monomer (C?H?X?, wherein ? and ? are natural numbers of 5 or more; ? is an integer including zero; X is O, N or F) having a boiling point of about 20° C. to about 350° C. which is not substituted by a vinyl group or an acetylene group; introducing the vaporized gas and CO2 gas or H2 gas into a CVD reaction chamber inside which a substrate is placed; and forming a hydrocarbon-containing polymer film on the substrate by plasma polymerization of the gas, thereby reducing extinction coefficient (k) at 193 nm and increasing mechanical hardness.

Abstract: A semiconductor device includes a substrate having a trench, a liner layer pattern on sidewalls and a bottom surface of the trench, the liner layer pattern including a first oxide layer pattern and a second oxide layer pattern, a diffusion blocking layer pattern on the liner layer pattern, and an isolation layer pattern in the trench on the diffusion blocking layer pattern.

Abstract: One embodiment of a method of fabricating a flash memory device includes forming a trench mask pattern, which includes a gate insulation pattern and a charge storage pattern stacked in sequence, on a semiconductor substrate; etching the semiconductor substrate using the trench mask pattern as an etch mask to form trenches defining active regions; and sequentially forming lower and upper device isolation patterns in the trench. After sequentially forming an intergate insulation film and a control gate film on the upper device isolation pattern, the control gate film, the intergate insulation pattern and the gloating gate pattern are formed, thereby providing gate lines crossing over the active regions.

Abstract: Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill recessed trench regions formed in the substrate. The first oxide layer and the SOG layer are then subjected to a planarization sequence including a CMP process followed by an etchback process to form a composite structure having a substantially flat upper surface that exposes both the oxide and the SOG material. The second oxide layer is then applied and subjected to a similar CMP/etchback sequence to obtain a composite structure having an upper surface that is recessed relative to a plane defined by the surfaces of adjacent active regions.

Abstract: In a method of forming a device isolation layer, a trench is formed in a substrate and a preliminary fin is formed on the substrate using a hard mask pattern on a surface of the substrate as an etching mask. A first thin layer is formed on the bottom and sides of the trench. A lower insulation pattern is formed in a lower portion of the trench on the first thin layer, and an upper insulation pattern is formed on the lower insulation pattern. The upper insulation pattern is etched away so that the first thin layer remains on a side surface of the preliminary fin. A device isolation layer is formed in the lower portion of the trench and a silicon fin is formed having a top surface thereof that is higher relative to a top surface of the device isolation layer.