Patents by Inventor Eun-Soo Jeong

Eun-Soo Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220348703
    Abstract: Provided is a method of preparing a vinyl chloride-acrylic copolymer latex. Specifically, in one embodiment of the present invention, provided is a method of preparing a latex including vinyl chloride-acrylic copolymer particles with a high degree of polymerization and high molecular weight by performing an emulsion polymerization of a vinyl chloride monomer and an acrylic monomer in the presence of an aqueous dispersion medium and an emulsifier while optimizing a feeding mode of the monomers and the emulsifier.
    Type: Application
    Filed: July 17, 2020
    Publication date: November 3, 2022
    Inventors: Eun Soo JEONG, Geun Chang RYU, Chulwoong Lee
  • Publication number: 20220348784
    Abstract: Provided is a method of preparing a vinyl chloride-vinyl acetate copolymer latex. Specifically, in one embodiment of the present invention, provided is a method of preparing a latex including vinyl chloride-vinyl acetate copolymer particles with a high degree of polymerization and molecular weight and a uniform particle composition by performing an emulsion polymerization of a vinyl chloride monomer and a vinyl acetate monomer in the presence of an aqueous dispersion medium and an emulsifier while optimizing a feeding mode of the vinyl chloride monomer and the emulsifier.
    Type: Application
    Filed: July 17, 2020
    Publication date: November 3, 2022
    Inventors: Eun Soo JEONG, Geun Chang RYU, Chulwoong LEE
  • Publication number: 20220278416
    Abstract: A battery cell includes: an electrode assembly; a battery case accommodating the electrode assembly and an electrolyte; and a gas discharging portion disposed between the electrode assembly and the battery case, and opening and closing a flow path based on pressure within the battery case, wherein the gas discharging portion includes: a moving member being moved in the flow path; a plurality of elastic members each elastically supporting the moving member; and a plurality of support members each disposed between the moving member and the elastic member, and in point contact with the moving member.
    Type: Application
    Filed: February 25, 2022
    Publication date: September 1, 2022
    Inventors: Taek Eon JEONG, Sang Mo KIM, Dong Ju KIM, Jae Gyu BYUN, Sun Min PARK, Eun Soo CHO
  • Publication number: 20220090185
    Abstract: Disclosed herein is a method for determining a false positive by a real-time nucleic acid amplification reaction, including steps of a) preparing a positive control including a positive control gene including a target gene sequence and a contamination-determining gene sequence, b) obtaining a gene from a sample to prepare a group to be tested, followed by adding an internal control gene to the group to be tested, and c) adding probes capable of binding to each of a target gene, a contamination-determining gene and the internal control gene respectively to the positive control and the group to be tested, followed by proceeding a real-time nucleic acid amplification reaction (PCR), and characterized in that fluorescent light is emitted at the same wavelength when the probes capable of binding to each of the contamination-determining gene and the internal control gene are hydrolyzed.
    Type: Application
    Filed: September 10, 2021
    Publication date: March 24, 2022
    Inventors: Eun-Soo JEONG, Hye-Min LEE, Jae-Hyun AHN
  • Publication number: 20200353393
    Abstract: A nucleic acid purification device according to the inventive concept includes an activated carbon fiber filter, wherein the activated carbon fiber filter includes an activated carbon fiber and a potassium compound coated on the surface of the activated carbon fiber.
    Type: Application
    Filed: May 7, 2020
    Publication date: November 12, 2020
    Applicants: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, Cancer Rop Co., Ltd.
    Inventors: Eun-Soo JEONG, MIN SEON KIM, Kwang Hyo CHUNG
  • Patent number: 8099842
    Abstract: According to the present application, a method of manufacturing a piezoelectric transistor may include forming a cavity over a substrate, such as a semiconductor substrate. The method may include depositing and patterning metal material over a portion of a cavity, and may include depositing an oxide film over a cavity and/or patterned metal material. Piezoelectric material may be deposited over an oxide film and patterned to avoid connection with metal material. The method may include depositing a second oxide film over a substrate including piezoelectric material. Metal wiring may be formed and may apply voltage to piezoelectric material that may be in contact with a semiconductor substrate.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: January 24, 2012
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Eun-Soo Jeong
  • Patent number: 7977142
    Abstract: A method of manufacturing an image sensor having a minimized spatial distance between microlenses to improve integration, and thus, enhance the ability of each microlens to condense light incident.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: July 12, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Eun-Soo Jeong
  • Patent number: 7973374
    Abstract: Embodiments relate to a semiconductor device and a method for fabricating the same. According to embodiments, a semiconductor device may include a metal film spaced from a semiconductor substrate at a predetermined interval and in which a plurality of etching holes are formed. A bottom metal pattern disposed on and/or over a space between the semiconductor substrate and metal film and top metal pattern formed on and/or over the bottom metal pattern may be provided. A pillar may be formed on and/or over the semiconductor substrate and may support one side of a low surface of the bottom metal pattern. A pad may be formed on and/or over the semiconductor substrate, and an air layer corresponding to the bottom metal pattern may be inserted therein. According to embodiments, a pyro-electric switch transistor using a bi-metal with different coefficients of thermal expansion may be provided.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: July 5, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Eun-Soo Jeong
  • Patent number: 7943521
    Abstract: A method for patterning a semiconductor device can include forming a conductive layer over a semiconductor substrate; alternatively forming positive photoresists and negative photoresists over the conductive layer, forming a plurality of first conductive lines by selectively removing a portion of the conductive layer using the positive photoresist and the negative photoresist as masks; forming an oxide film over the semiconductor substrate including the first conductive lines and the conductive layer; performing a planarization process over the oxide film using the uppermost surface of the first conductive line as a target; removing the plurality of first conductive lines using the oxide film as a mask; forming a plurality if trenches in the semiconductor substrate and removing a portion of the oxide film to expose the uppermost surface of the conductive layer; and then forming a plurality of second conductive lines by removing the exposed conductive layer using the oxide film as a mask.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: May 17, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Eun-Soo Jeong
  • Patent number: 7879719
    Abstract: A semiconductor device and a method for manufacturing the device that minimizes a line width while maximizing integration density of the semiconductor device. The method includes forming an interlayer insulating film on a semiconductor substrate, and then forming a first via hole in the interlayer insulating film, and then forming a resin material in the first via hole, and then forming a plurality of second via holes in the interlayer insulating film laterally, and then forming a resin material in the second via holes, and then simultaneously forming a plurality of third via holes in the interlayer insulating film and a trench spatially above and corresponding to the first via hole, and then removing the resin formed in the first via hole and the second via holes, and then simultaneously forming metal layers in the first via hole and the second and third via holes and the trench.
    Type: Grant
    Filed: December 14, 2008
    Date of Patent: February 1, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Eun-Soo Jeong
  • Patent number: 7867834
    Abstract: A manufacturing method of a semiconductor device according to an embodiment includes: forming a trench for a device isolation area and a semiconductor projection with a first width by etching a semiconductor substrate; forming an oxide film on the trench and the semiconductor projections; forming an insulating layer on the oxide film; exposing the upper surface of the semiconductor projection by polishing the insulating layer and the oxide film; forming a gate insulating layer at a lower region of the semiconductor projection; and etching the insulating layer and the oxide film on the substrate.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: January 11, 2011
    Assignee: Dongbu Hitek Co., Ltd.
    Inventors: Eun Soo Jeong, Jea Hee Kim
  • Patent number: 7858516
    Abstract: A method for forming a fine pattern of a semiconductor device which includes sequentially forming a non-etching layer and a sacrificial layer on a semiconductor substrate; and then forming a plurality of photo-resist layer patterns having a plurality of openings exposing the sacrificial layer; and then forming a plurality of first pattern grooves in the sacrificial layer etching the exposed sacrificial layer using the photo-resist patterns as an etching barrier; removing the photo-resist layer; and then forming an oxidation layer having a plurality of second pattern grooves on the sacrificial layer and in the first pattern grooves by performing a thermal oxidation process on the sacrificial layer; and then forming a plurality of first through-holes exposing the non-etching layer by completely removing the sacrificial layer remaining in oxidation layer; and then forming a plurality of patterns in the non-etching layer by etching the exposed portions of the non-etching layer using the oxidation layer as an etch
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: December 28, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Eun-Soo Jeong
  • Patent number: 7838435
    Abstract: A method for forming a fine-pitch pattern on a semiconductor substrate is provided. The method includes patterning the semiconductor substrate to form a plurality of fine lines, forming a thermal oxide layer on the fine lines, polishing the thermal oxide layer to expose a top surface of the fine lines; etching the fine lines using the thermal oxide layer as a mask to expose first portions of the semiconductor substrate, etching a central bottom portion of the thermal oxide layer to expose second portions of the semiconductor substrate, and etching the semiconductor substrate using the etched thermal oxide layer as a mask.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: November 23, 2010
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Eun Soo Jeong
  • Patent number: 7741212
    Abstract: A semiconductor device and method for manufacturing the same are provided, capable of narrowing feature size by utilizing the property of oxidation of a material. In one method, a polysilicon layer can be patterned into a fine pattern up to a critical dimension using a photolithography process. Then the patterned polysilicon layer can be oxidized, thereby narrowing the gap between adjacent polysilicon patterns and narrowing the polysilicon patterns through the oxidation process. The narrowed polysilicon patterns and/or the narrowed gap between adjacent polysilicon patterns can be used to form vias or trenches in the substrate (or layer) below the polysilicon layer having a width narrower than the critical dimension.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: June 22, 2010
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Eun Soo Jeong
  • Publication number: 20100060104
    Abstract: A piezoelectric transistor including a substrate, such as a semiconductor substrate. The substrate may include a cavity and the cavity may be etched downward. A piezoelectric transistor may include piezoelectric material formed over the semiconductor substrate in a cantilever form, and may be elastically strained up and/or down. A piezoelectric transistor may include metal material electrically connected to the piezoelectric material by the piezoelectric effect, and metal wiring may supply voltage to piezoelectric material. Methods of fabricating the same are disclosed.
    Type: Application
    Filed: September 4, 2009
    Publication date: March 11, 2010
    Inventor: Eun-Soo Jeong
  • Patent number: D957376
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: July 12, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-Yong Song, Byoung-Jin Kim, Jung-Hyun Choi, Woo-Hyeok Jeong, Eun-Soo Kim
  • Patent number: D957382
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: July 12, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-Yong Song, Byoung-Jin Kim, Jung-Hyun Choi, Woo-Hyeok Jeong, Eun-Soo Kim
  • Patent number: D962189
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: August 30, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-Yong Song, Byoung-Jin Kim, Jung-Hyun Choi, Woo-Hyeok Jeong, Eun-Soo Kim
  • Patent number: D965545
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: October 4, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-Yong Song, Byoung-Jin Kim, Jung-Hyun Choi, Woo-Hyeok Jeong, Eun-Soo Kim
  • Patent number: D965547
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: October 4, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-Yong Song, Byoung-Jin Kim, Jung-Hyun Choi, Woo-Hyeok Jeong, Eun-Soo Kim