Patents by Inventor Eun-Sun AN

Eun-Sun AN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230047113
    Abstract: Provided are a polishing device including: a surface plate; a polishing pad mounted on the surface plate; a carrier for accommodating a polishing object; and a slurry supply unit including at least one nozzle, wherein the carrier performs a vibrating motion in a trajectory from the center of the surface plate to the end of the surface plate, and the slurry supply unit performs a vibrating motion at the same trajectory and speed as those of the vibrating motion of the carrier, as a polishing device which includes a slurry supply unit enabling subdivided driving in the supply of a polishing slurry, and in which the driving of the slurry supply unit has an advantage enabling optimized driving in an organic relationship between rotation and/or vibrating motion of the carrier and the surface plate and vertical pressurization conditions, etc. for the polishing surface of the carrier.
    Type: Application
    Filed: August 12, 2022
    Publication date: February 16, 2023
    Inventors: Jae In AHN, Jong Wook YUN, Eun Sun JOENG, Jang Won SEO
  • Publication number: 20230040931
    Abstract: Provided is a polishing composition for a semiconductor process comprising abrasive particles, the abrasive particles containing an amine-based polishing rate improver, and comprising the amine-based polishing rate improver. Provided is a polishing composition for a semiconductor process further comprising an amine-based surface modifier around the surface of the abrasive particles, wherein the sum of the content of an amine group contained in the amine-based polishing rate improver and the content of an amine group contained in the amine-based surface modifier is 0.0185% by weight or more based on the total composition weight. The polishing composition for a semiconductor process may implement the polishing rate and defect prevention performance within a target range in polishing the boron-doped polysilicon layer.
    Type: Application
    Filed: July 21, 2022
    Publication date: February 9, 2023
    Inventors: Seung Chul HONG, Deok Su Han, Han Teo Park, Kyu Hun Kim, Eun Sun Joeng, Jang Kuk Kwon, Hyeong Ju Lee
  • Publication number: 20230030484
    Abstract: A printed circuit board includes: a first insulating layer having a recess portion in one surface of the first insulating layer; a first circuit pattern embedded in the first insulating layer and being in contact with a lower surface of the recess portion; a second insulating layer disposed on the one surface of the first insulating layer to be disposed in at least a portion of the recess portion; and a via penetrating through at least a portion of the second insulating layer, disposed in the recess portion, and connected to the first circuit pattern.
    Type: Application
    Filed: May 18, 2022
    Publication date: February 2, 2023
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yong Wan Ji, Jin Uk Lee, Eun Sun Kim, Young Hun You
  • Patent number: 11569455
    Abstract: A compound for an organic optoelectronic device, an organic optoelectronic device including the same, and a display device, the compound being represented by Chemical Formula 1:
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: January 31, 2023
    Assignee: SAMSUNG SDI CO., LTD.
    Inventors: Jun Seok Kim, Dong Min Kang, Dongyeong Kim, Namheon Lee, Byoungkwan Lee, Sangshin Lee, Jihun Shin, Eun Sun Yu, Yoonman Lee
  • Patent number: 11563179
    Abstract: The present invention relates to a compound represented by formula 1, an organic optoelectronic element comprising the same, and a display device comprising the organic optoeletric element. Formula 1 and the description regarding the samen are as defined in the specification.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: January 24, 2023
    Assignee: SAMSUNG SDI CO., LTD.
    Inventors: Dong-Wan Ryu, Young-Kyoung Jo, Sung-Hyun Jung, Chang-Ju Shin, Han-Ill Lee, Eui-Su Kang, Chang-Woo Kim, Min-Jee Park, Eun-Sun Yu, Pyeong-Seok Cho
  • Patent number: 11558959
    Abstract: A printed circuit board includes an insulating layer, a circuit pattern embedded in the insulating layer and including a first metal layer, a second metal layer and a third metal layer disposed between the first metal layer and the second metal layer, and a connection conductor disposed on one surface of the insulating layer and connected to the circuit pattern, wherein the first metal layer is exposed through the one surface of the insulating layer.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: January 17, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jin Uk Lee, Sangik Cho, Eun Sun Kim, Young Hun You, Jong Eun Park
  • Patent number: 11548970
    Abstract: In the composition according to the embodiment, the content of an unreacted diisocyanate monomer in a urethane-based prepolymer may be controlled to control the physical properties thereof such as gelation time. Thus, since the micropore characteristics, polishing rate, and pad cut rate of a polishing pad obtained by curing the composition according to the embodiment may be controlled, it is possible to efficiently manufacture high-quality semiconductor devices using the polishing pad.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: January 10, 2023
    Assignee: SKC solmics Co., Ltd.
    Inventors: Eun Sun Joeng, Hye Young Heo, Jang Won Seo, Jong Wook Yun
  • Publication number: 20220410337
    Abstract: The present invention relates to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, to a process for preparing the same, and to a process for preparing a semiconductor device using the same. The polishing pad according to an embodiment can achieve low hardness by comprising a polishing layer formed using a curing agent of specific components. It is possible to enhance the mechanical properties of the polishing pad, as well as to improve the surface defects appearing on the surface of a semiconductor substrate, by controlling the surface roughness reduction rate and the recovery elasticity index of the polishing pad to specific ranges. It is also possible to further enhance the polishing rate.
    Type: Application
    Filed: April 28, 2022
    Publication date: December 29, 2022
    Inventors: Jong Wook YUN, Eun Sun Joeng, Jangwon Seo, Hyeyoung Heo
  • Patent number: 11535610
    Abstract: The present invention relates to a pidolate salt and malate salt of a compound represented by a formula 1 with an excellent liquid-phase stability, solid-phase stability, water solubility, precipitation stability and hygroscopicity all together as a compound for preventing and treating diseases mediated by an acid pump antagonistic activity, as well as a method for preparing the same.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: December 27, 2022
    Assignee: HK INNO.N CORPORATION
    Inventors: Eun Sun Kim, Min Kyoung Lee, Sung Ah Lee, Kwang Do Choi, Jae Sun Kim, Hyung Chul Yoo
  • Patent number: 11534887
    Abstract: Embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductor devices. The polishing pad may secure excellent polishing rate and within-wafer non-uniformity by controlling the physical properties such as initial load resistivity and compressive elasticity of the cushion layer and/or the laminate as defined by Equations 1 and 2: L ? R L ? ( % ) = T ? 1 ? L - T ? 2 ? L T ? 1 ? L - T ? 3 ? L × 100 [ Equation ? ? 1 ] C ? E L ? ( % ) = T ? 4 ? L - T ? 3 ? L T ? 2 ? L - T ? 3 ? L × 1 ? 00.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: December 27, 2022
    Assignee: SKC SOLMICS CO., LTD.
    Inventors: Jangwon Seo, Eun Sun Joeng, Jong Wook Yun
  • Patent number: 11532801
    Abstract: The present invention relates to an organic electroluminescent device, particularly to an organic light emitting diode (OLED) including an ETL stack of at least two electron transport layers, wherein the first electron transport layer comprises a first electron transport matrix compound and the second electron transport layer comprises second electron transport matrix compound and a redox n-dopant, and a device comprising the OLED.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: December 20, 2022
    Assignees: Novaled GmbH, Samsung SDI Co. Ltd.
    Inventors: Domagoj Pavicic, Jerome Ganier, Vygintas Jankus, Hyungsun Kim, Byungku Kim, Youngkwon Kim, Younhwan Kim, Hun Kim, Eun Sun Yu, Sung-Hyun Jung
  • Publication number: 20220371155
    Abstract: The present disclosure relates to a polishing pad, a method for manufacturing the polishing pad, and a method for manufacturing a semiconductor device using the polishing pad, and the present disclosure can prevent an error in detecting the end point due to the window in the polishing pad by minimizing the effect on transmittance according to the surface roughness of the window in the polishing pad in the polishing process, and allows the fluidity and loading rate of the polishing slurry in the polishing process to be implemented at similar levels by maintaining the surface roughness difference between the polishing layer and the window in the polishing pad within the predetermined range, thereby enabling the problem of deterioration of polishing performance due to the surface difference between the polishing layer and the window to be prevented. Further, a method for manufacturing a semiconductor device to which a polishing pad is applied may be provided.
    Type: Application
    Filed: May 3, 2022
    Publication date: November 24, 2022
    Inventors: Sung Hoon YUN, Jae In AHN, Eun Sun Joeng, Jang Won Seo
  • Publication number: 20220355436
    Abstract: A polishing pad includes a polishing layer, wherein the polishing layer includes zinc (Zn), and a concentration of the zinc (Zn) is 0.5 ppm to 40 ppm parts by weight based on the total weight of the polishing layer. In an exemplary embodiment, a polishing pad is provided wherein a concentration of the zinc (Zn) is 0.5 ppm to 40 ppm parts by weight based on the total weight of the polishing layer, a concentration of the iron (Fe) is 1 ppm to 50 ppm parts by weight based on the total weight of the polishing layer, and a concentration of the aluminum (Al) is 2 ppm to 50 ppm parts by weight based on the total weight of the polishing layer.
    Type: Application
    Filed: May 4, 2022
    Publication date: November 10, 2022
    Inventors: Eun Sun JOENG, Jong Wook YUN, Jang Won SEO, Su Young MOON
  • Patent number: 11482682
    Abstract: Disclosed are a compound for an organic optoelectronic diode, a composition for an organic optoelectronic diode, including the compound for the organic optoelectronic diode, an organic optoelectronic diode including the same, and a display device.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: October 25, 2022
    Assignee: SAMSUNG SDI CO., LTD.
    Inventors: Chang Ju Shin, Changwoo Kim, Hyung Sun Kim, Dong Wan Ryu, Seungjae Lee, Yuna Jang, Dong Min Kang, Eun Sun Yu, Hanill Lee, Sung-Hyun Jung, Juyeon Jung, Ho Kuk Jung
  • Publication number: 20220322533
    Abstract: A printed circuit board includes a first insulating layer; a protective filler layer disposed on one surface of the first insulating layer; a first wiring layer disposed on the one surface of the first insulating layer and having a pad protruding with respect to the protective filler layer; a first via passing through the first insulating layer and contacting the pad; and a second insulating layer disposed on the first wiring layer and the protective filler layer, and having a cavity exposing the pad and at least a portion of the protective filler layer, respectively.
    Type: Application
    Filed: September 16, 2021
    Publication date: October 6, 2022
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Eun Sun Kim, Jin Uk Lee, Young Hun You, Chi Seong Kim
  • Publication number: 20220322528
    Abstract: A printed circuit board includes a first insulating layer; a first wiring layer disposed on one surface of the first insulating layer and including a pad; a second insulating layer disposed on the one surface of the first insulating layer and covering the first wiring layer; a second wiring layer disposed on one surface of the second insulating layer and including a metal pattern; a third insulating layer disposed on the one surface of the second insulating layer and covering the second wiring layer; and a cavity extending through each of the second and third insulating layers, and having a bottom surface and a sidewall respectively exposing the pad of the first wiring layer and the metal pattern of the second wiring layer. The cavity includes a non-through groove in the one surface of the first insulating layer.
    Type: Application
    Filed: September 15, 2021
    Publication date: October 6, 2022
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Eun Sun KIM, Jin Uk LEE, Young Hun YOU
  • Publication number: 20220322525
    Abstract: A printed circuit board includes a first insulating layer, a first conductor-pattern layer disposed on one surface of the first insulating layer, a first recess formed in the other surface of the first insulating layer opposing one surface of the first insulating layer, a second conductor-pattern layer disposed in the first recess, and a first metal post penetrating the first insulating layer, connecting the first and second conductor-pattern layers to each other, and having one end exposed to a bottom surface of the first recess, wherein the second conductor-pattern layer includes a seed layer disposed on at least a portion of each of a surface of one end of the first metal post exposed to the bottom surface of the first recess and an internal surface of the first recess including the bottom surface of the first recess, and a plating layer disposed on the seed layer to fill at least a portion of the first recess.
    Type: Application
    Filed: September 8, 2021
    Publication date: October 6, 2022
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jin Uk Lee, Sangik Cho, Chi Won Hwang, Eun Sun Kim
  • Publication number: 20220296204
    Abstract: A digestive canal scanning device of the present invention includes a sensor module, a data processing unit, and an analysis unit. A body scanning device of the present invention includes a sensor module, a data processing unit, and an analysis unit. An acoustic digestive organ monitoring system of the present invention includes an auscultation unit, an artifact collection unit, a signal extraction unit, a feature extraction unit, a database, an artificial neural network, and a wireless communication unit.
    Type: Application
    Filed: April 2, 2020
    Publication date: September 22, 2022
    Applicant: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Eun-sun KIM, Seung-Jong KIM, Yongdoo PARK
  • Patent number: D964954
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: September 27, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Minsoo Kwon, Eun Sun Chae, Aejung Seo
  • Patent number: D964955
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: September 27, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Minsoo Kwon, Eun Sun Chae, Aejung Seo