Abstract: A semiconductor device includes: a standard cell array including a plurality of standard cells, each of the plurality of standard cells; a plurality of power supply lines configured to provide a power supply voltage and extending in a first direction; a capacitor structure including electrode structures included in each of a plurality of dielectric layers formed on the standard cell array, the capacitor structure having vias connecting the electrode structures; and contacts electrically connecting the capacitor structure and the standard cell array to each other. Each of the plurality of standard cells provides a unit capacitor circuit having capacitance that is based on a connection structure of active regions and gates of first and second transistors thereof.

Abstract: Described herein are chemical mechanical polishing (CMP) slurry compositions, such as CMP slurry compositions for polishing an indium tin oxide (ITO) layer, along with methods of fabricating a semiconductor device using such a CMP slurry composition. The CMP slurry composition can include a polishing particle, a dispersing agent, an auxiliary oxidizing agent, and a sugar alcohol compound.

Abstract: Described herein are chemical mechanical polishing (CMP) slurry compositions, such as CMP slurry compositions for polishing an indium tin oxide (ITO) layer, along with methods of fabricating a semiconductor device using such a CMP slurry composition. The CMP slurry composition can include a polishing particle, a dispersing agent, an auxiliary oxidizing agent, and a sugar alcohol compound.

Abstract: A semiconductor memory device includes a cell array that includes a plurality of DRAM cells to store data, and refresh control logic that refreshes the plurality of DRAM cells depending on access scenario information provided from an outside. The refresh control logic determines a refresh time of the plurality of DRAM cells with reference to the access scenario information and a retention characteristic of the plurality of DRAM cells and refreshes the plurality of DRAM cells depending on the determined refresh time.

Abstract: A semiconductor memory device includes a cell array that includes a plurality of DRAM cells to store data, and refresh control logic that refreshes the plurality of DRAM cells depending on access scenario information provided from an outside. The refresh control logic determines a refresh time of the plurality of DRAM cells with reference to the access scenario information and a retention characteristic of the plurality of DRAM cells and refreshes the plurality of DRAM cells depending on the determined refresh time.

Abstract: A semiconductor package includes a logic chip mounted on a substrate, a first memory chip disposed on the logic chip, which includes a first active surface, and a second memory chip disposed on the first memory chip. The second memory chip is disposed on the first memory chip in such a way that the first memory chip and second memory chip are offset from each other. The second memory chip has a second active surface. The first active surface and the second active surface face each other and are electrically connected to each other through a first solder bump.

Abstract: Disclosed is a projector, the projector including a light source, an illumination unit illuminating light incident from the light source, and a display device enabling to realize an image by receiving the light irradiated from the illumination unit, and whose center is positioned at an axis different from an optical axis of the illumination unit.

Abstract: A semiconductor package includes a logic chip mounted on a substrate, a first memory chip disposed on the logic chip, which includes a first active surface, and a second memory chip disposed on the first memory chip. The second memory chip is disposed on the first memory chip in such a way that the first memory chip and second memory chip are offset from each other. The second memory chip has a second active surface. The first active surface and the second active surface face each other and are electrically connected to each other through a first solder bump.

Abstract: A memory device comprises at least two memory ranks sharing input/output lines, at least one mode register configured to store bits used to tune delays of data signals of the at least two ranks output through the input/output lines, a controller configured to determine tuning parameters for the data signals based on the stored bits in the at least one mode register, the tuning parameters comprising at least the delays of the data signals, and at least one nonvolatile memory disposed in at least one of the at least two memory ranks and configured to store the tuning parameters.

Abstract: A memory device comprises at least two memory ranks sharing input/output lines, at least one mode register configured to store bits used to tune delays of data signals of the at least two ranks output through the input/output lines, a controller configured to determine tuning parameters for the data signals based on the stored bits in the at least one mode register, the tuning parameters comprising at least the delays of the data signals, and at least one nonvolatile memory disposed in at least one of the at least two memory ranks and configured to store the tuning parameters.

Abstract: A memory device comprises at least two memory ranks sharing input/output lines, at least one mode register configured to store bits used to tune delays of data signals of the at least two ranks output through the input/output lines, a controller configured to determine tuning parameters for the data signals based on the stored bits in the at least one mode register, the tuning parameters comprising at least the delays of the data signals, and at least one nonvolatile memory disposed in at least one of the at least two memory ranks and configured to store the tuning parameters.

Abstract: Disclosed is a projector, the projector including a light source, an illumination unit illuminating light incident from the light source, and a display device enabling to realize an image by receiving the light irradiated from the illumination unit, and whose center is positioned at an axis different from an optical axis of the illumination unit.

Abstract: A projector optical system is provided, the system including an illumination unit including illumination lenses illuminating light downwards, a display device receiving light illuminated from the illumination lenses to enable to realize an image, projection lenses downwardly projecting light emitted from the display device to a screen, and a field lens changing an optical angle of the light illuminated from the illumination lenses and emitting the light to the display device, and changing an optical angle by receiving an image light of the display device and emitting the light to the projection lenses.

Abstract: The present disclosure relates to a polarization converting device and a method for manufacturing the same, wherein the polarization converting device includes a polarization separation unit aligned with a plurality of unit blocks including an optical separator transmitting a first polarization between an upper surface and a lower surface and reflecting a second polarization, and a phase retarder aligned in correspondence to an upper surface of each unit block of the polarization separation unit where a first region and a second region are alternately formed, wherein any one of the first and second regions of the phase retarder converts the polarized light while the other region emits the polarized light as it is.

Abstract: A projection system is characterized by: a first light source unit and a second light source unit selectively driven in response to operation mode; a light transmitting unit transmitting light emitted from the first light source unit or the second light source unit in the form of surface light; an image generator generating an image in response to an image signal using the light transmitted from the light transmitting unit; and a projection lens system projecting the image by enlarging the image generated by the image generator and projecting the enlarged image.

Abstract: A memory device comprises at least two memory ranks sharing input/output lines, at least one mode register configured to store bits used to tune delays of data signals of the at least two ranks output through the input/output lines, a controller configured to determine tuning parameters for the data signals based on the stored bits in the at least one mode register, the tuning parameters comprising at least the delays of the data signals, and at least one nonvolatile memory disposed in at least one of the at least two memory ranks and configured to store the tuning parameters.

Abstract: Disclosed is a projector, the projector including a light source, an illumination unit illuminating light incident from the light source, and a display device enabling to realize an image by receiving the light irradiated from the illumination unit, and whose center is positioned at an axis different from an optical axis of the illumination unit.

Abstract: Disclosed is a polarization conversion apparatus, the apparatus including a first optical device capable of angle-converting incident unpolarized light to allow a polarization direction to be emitted in mutually different first and second linear polarizations, an FEL (Fly Eye Lens) including first and second MLAs (Micro Lens Arrays) arrayed with first and second micro lenses, where first and second linear polarizations of the first optical device incident on the first micro lenses are divided and condensed on an upper side and a bottom side of the second micro lenses of the second MLA, and a second optical device converting the first and second linear polarizations condensed on the upper side or the bottom side of the second MLA at the FEL to any one polarization of the first and second linear polarizations and emitting the polarization.

Abstract: A projection system is disclosed, the projection system including: an illumination unit; a PBS (Polarizing Beam Splitter) reflecting the light from the illumination unit, transmitting an image light, having a width larger than that of entrance pupil through which the image light is incident, and having a structure in which a width of an area facing projection lenses is larger than that of an area perpendicular to an area facing the projection lenses; a display device receiving the light reflected from the PBS and outputting the light as an image light; and a projection unit mounted with the projection lenses for projecting the image light outputted from the display device to a screen.

Abstract: A redundancy memory cell access circuit includes a first control unit, a second control unit, and an accessing unit. The first control unit compares an unprogrammed fuse signal with an address signal to generate a first redundancy enable signal from the comparison. The accessing unit allows access to a redundancy memory cell corresponding to the unprogrammed signal when the first redundancy enable signal from the first control unit or a second redundancy enable signal from the second control unit is activated. Thus, the redundancy memory cell access circuit is tested simultaneously with testing of the redundancy memory cell for minimized testing and programming times.