Patents by Inventor Eun-Ji Choi

Eun-Ji Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12206117
    Abstract: The present disclosure relates to a method for manufacturing core-shell particles using carbon monoxide, and more particularly, to a method for manufacturing core-shell particles, the method of which a simple and fast one-pot reaction enables particle manufacturing to reduce process costs, facilitate scale-up, change various types of core and shell metals, and form a multi-layered shell by including the steps of adsorbing carbon monoxide on a transition metal for a core, and reacting carbon monoxide adsorbed on the surface of the transition metal for the core, a metal precursor for a shell, and a solvent to form particles with a core-shell structure having a reduced metal shell layer formed on a transition metal core.
    Type: Grant
    Filed: September 12, 2023
    Date of Patent: January 21, 2025
    Assignee: Korea Institute of Energy Research
    Inventors: Gu-gon Park, Eun Jik Lee, Kyunghee Kim, Sung-dae Yim, Seok-hee Park, Min-ji Kim, Young-jun Sohn, Byungchan Bae, Seung-gon Kim, Dongwon Shin, Hwanyeong Oh, Seung Hee Woo, So Jeong Lee, Hyejin Lee, Yoon Young Choi, Won-yong Lee, Tae-hyun Yang
  • Publication number: 20250023530
    Abstract: A receiver circuit includes a first amplification stage and a second amplification stage. The first amplification stage is configured to generate a first output signal by differentially amplifying an input signal pair. The second amplification stage is configured to generate a second output signal by amplifying the first output signal. The receiver circuit is configured to deactivate the second amplification stage and then deactivate the first amplification stage.
    Type: Application
    Filed: December 12, 2023
    Publication date: January 16, 2025
    Applicant: SK hynix Inc.
    Inventors: Jun Seo JANG, Bon Kwang KOO, Beom Kyu SEO, Soon Sung AN, Sung Hwa OK, Eun Ji CHOI, Jae Hyeong HONG
  • Publication number: 20250006231
    Abstract: A transceiver includes a first inverter chain configured to deliver a signal in response to an enable signal and a second inverter chain which is coupled to the first inverter chain in parallel and configured to output a reset value of the signal in response to an inverted enable signal.
    Type: Application
    Filed: November 2, 2023
    Publication date: January 2, 2025
    Inventors: Jun Seo JANG, Sung Hwa OK, Eun Ji CHOI, Jae Hyeong HONG
  • Publication number: 20240355376
    Abstract: A voltage generation circuit includes a voltage generation unit configured to generate a reference voltage using a power supply voltage and output the reference voltage through a voltage output node. The voltage generation circuit also includes a pre-charge unit configured to drive the voltage output node using the power supply voltage in response to a pre-charge control signal. The voltage generation circuit further includes a pre-charge control unit configured to generate at least one sampling voltage using the power supply voltage and generate the pre-charge control signal according to a result obtained by comparing the at least one sampling voltage with the reference voltage.
    Type: Application
    Filed: August 23, 2023
    Publication date: October 24, 2024
    Applicant: SK hynix Inc.
    Inventors: Jae Hyeong HONG, In Seok KONG, Bon Kwang KOO, Gwan Woo KIM, Heon Ki KIM, Beom Kyu SEO, Keun Seon AHN, Soon Sung AN, Sung Hwa OK, Jung Yeop LEE, Ji Young LEE, Dong Wook JANG, Jun Seo JANG, Sun Ki CHO, Eun Ji CHOI
  • Patent number: 11908543
    Abstract: The present technology may include a first detection unit configured to generate an output signal by detecting a level of an input terminal in response to a transition of a control clock signal during a normal read operation, and a second detection unit configured to generate the output signal by detecting the level of the input terminal regardless of the transition of the control clock signal during a state information read operation.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: February 20, 2024
    Assignee: SK hynix Inc.
    Inventors: Eun Ji Choi, Keun Seon Ahn, Kwan Su Shon, Yo Han Jeong
  • Publication number: 20240014816
    Abstract: An impedance calibration circuit includes a first leg set having an impedance calibrated to a first target impedance according to an impedance control code during an activation period of a first timing control signal, a second leg set having an impedance calibrated to a second target impedance according to the impedance control code during an activation period of a second timing control signal, a code generation circuit configured to calibrate and output a value of the impedance control code according to a result of comparing a voltage of a node, to which the first leg set is connected, with a reference voltage, and a timing control signal generation circuit configured to generate the first timing control signal and the second timing control signal having different activation periods in response to an impedance calibration enable signal.
    Type: Application
    Filed: December 20, 2022
    Publication date: January 11, 2024
    Applicant: SK hynix Inc.
    Inventor: Eun Ji CHOI
  • Patent number: 11837310
    Abstract: The present disclosure relates to a memory device for correcting a pulse duty ratio and a memory system including the same, and relates to a memory device which corrects the duty ratio of a primary pulse of a memory device control signal, and a memory system including the same.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: December 5, 2023
    Assignee: SK hynix Inc.
    Inventors: Jaehyeong Hong, In Seok Kong, Gwan Woo Kim, Jae Young Park, Kwan Su Shon, Soon Sung An, Daeho Yang, Sung Hwa Ok, Junseo Jang, Yo Han Jeong, Eun Ji Choi
  • Patent number: 11799481
    Abstract: The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: October 24, 2023
    Assignee: SK hynix Inc.
    Inventors: Jin Ha Hwang, Yo Han Jeong, Eun Ji Choi
  • Patent number: 11631445
    Abstract: A semiconductor apparatus includes a memory controller and data storage configured to input and output data in synchronization with a clock signal provided from the memory controller. The data storage includes a memory cell array and a data output apparatus configure to output read data from the memory cell array by sensing a logic level of the read data during a low-level period of a first clock, which is an inverted signal of a divided clock of the clock signal, and a low-level period of a second clock, the second clock having a set to phase delay amount from the divided clock.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: April 18, 2023
    Assignee: SK hynix Inc.
    Inventor: Eun Ji Choi
  • Publication number: 20230111807
    Abstract: The present technology may include a first detection unit configured to generate an output signal by detecting a level of an input terminal in response to a transition of a control clock signal during a normal read operation, and a second detection unit configured to generate the output signal by detecting the level of the input terminal regardless of the transition of the control clock signal during a state information read operation.
    Type: Application
    Filed: March 24, 2022
    Publication date: April 13, 2023
    Applicant: SK hynix Inc.
    Inventors: Eun Ji CHOI, Keun Seon AHN, Kwan Su SHON, Yo Han JEONG
  • Publication number: 20230056686
    Abstract: The present disclosure relates to a memory device for correcting a pulse duty ratio and a memory system including the same, and relates to a memory device which corrects the duty ratio of a primary pulse of a memory device control signal, and a memory system including the same.
    Type: Application
    Filed: January 5, 2022
    Publication date: February 23, 2023
    Inventors: Jaehyeong HONG, In Seok KONG, Gwan Woo KIM, Jae Young PARK, Kwan Su SHON, Soon Sung AN, Daeho YANG, Sung Hwa OK, Junseo JANG, Yo Han JEONG, Eun Ji CHOI
  • Patent number: 11551733
    Abstract: The present technology includes a data strobe clock output circuit. The data strobe clock output circuit includes a first output circuit configured to generate a rising clock and a falling clock in response to a clock and a first enable signal and output a first data strobe clock in response to the rising clock, the falling clock, and mode signals, and a second output circuit configured to generate a rising inverted clock and a falling inverted clock by inverting the rising clock and the falling clock generated by the first output circuit, and output a second data strobe clock in response to the rising inverted clock, the falling inverted clock, a second enable signal, and the mode signals.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: January 10, 2023
    Assignee: SK hynix Inc.
    Inventors: Eun Ji Choi, Ja Yoon Goo, Sung Hwa Ok
  • Publication number: 20220223188
    Abstract: A semiconductor apparatus includes a memory controller and data storage configured to input and output data in synchronization with a clock signal provided from the memory controller. The data storage includes a memory cell array and a data output apparatus configure to output read data from the memory cell array by sensing a logic level of the read data during a low-level period of a first clock, which is an inverted signal of a divided clock of the clock signal, and a low-level period of a second clock, the second clock having a set to phase delay amount from the divided clock.
    Type: Application
    Filed: June 7, 2021
    Publication date: July 14, 2022
    Applicant: SK hynix Inc.
    Inventor: Eun Ji CHOI
  • Publication number: 20220103176
    Abstract: The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.
    Type: Application
    Filed: December 13, 2021
    Publication date: March 31, 2022
    Applicant: SK hynix Inc.
    Inventors: Jin Ha HWANG, Yo Han JEONG, Eun Ji CHOI
  • Patent number: 11264064
    Abstract: A data driving circuit may include a trigger circuit and a pre-driver. The trigger circuit may be configured to block a remaining signal path among a plurality of signal paths for transmitting data except for a signal path corresponding to a currently selected driving strength. The pre-driver may be configured to drive data, which are transmitted through the signal path corresponding to the currently selected driving strength, using an impedance determined in accordance with a plurality of impedance control codes.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: March 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Eun Ji Choi
  • Patent number: 11233512
    Abstract: The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: January 25, 2022
    Assignee: SK hynix Inc.
    Inventors: Jin Ha Hwang, Yo Han Jeong, Eun Ji Choi
  • Publication number: 20220005513
    Abstract: The present technology includes a data strobe dock output circuit. The data strobe clock output circuit includes a first output circuit configured to generate a rising clock and a falling clock in response to a clock and a first enable signal and output a first data strobe clock in response to the rising clock, the falling clock, and mode signals, and a second output circuit configured to generate a rising inverted clock and a falling inverted clock by inverting the rising clock and the falling clock generated by the first output circuit, and output a second data strobe clock in response to the rising inverted clock, the falling inverted clock, a second enable signal, and the mode signals.
    Type: Application
    Filed: November 4, 2020
    Publication date: January 6, 2022
    Applicant: SK hynix Inc.
    Inventors: Eun Ji CHOI, Ja Yoon GOO, Sung Hwa OK
  • Patent number: 11190185
    Abstract: An impedance calibration circuit may include: a first driver having an impedance calibrated according to a first impedance control code, and configured to drive an output terminal according to first data; a second driver having an impedance calibrated according to a second impedance control code, and configured to drive the output terminal according to second data; and an impedance calibration circuit configured to calibrate the first impedance control code to a first target value set to a resistance value of an external resistor, and calibrate the second impedance control code to a second target value different from the resistance value of the external resistor.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: November 30, 2021
    Assignee: SK hynix Inc.
    Inventors: Eun Ji Choi, Jin Ha Hwang, Keun Seon Ahn, Yo Han Jeong
  • Publication number: 20210367600
    Abstract: The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.
    Type: Application
    Filed: September 10, 2020
    Publication date: November 25, 2021
    Applicant: SK hynix Inc.
    Inventors: Jin Ha HWANG, Yo Han JEONG, Eun Ji CHOI
  • Patent number: 11158356
    Abstract: Provided is a calibration circuit and operating method of the calibration circuit. A calibration circuit includes a first resistor code output circuit and a second resistor code output circuit. The first resistor code output circuit is coupled to an external resistor through an input/output pad, performs a first calibration operation, based on a first resistor value, such that a target voltage applied to a first reference node coupled to the input/output pad has a set voltage level, and outputs a first resistor code as a result obtained by performing the first calibration operation. The second resistor code output circuit receives the target voltage, sets an internal resistor value, based on the first resistor code, performs a second calibration operation, based on a second resistor value different from the first resistor value, and outputs a second resistor code as a result obtained by performing the second calibration operation. The first resistor value is a resistor value of the first resistor.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: October 26, 2021
    Assignee: SK hynix Inc.
    Inventors: Jin Ha Hwang, Kwan Su Shon, Keun Seon Ahn, Yo Han Jeong, Eun Ji Choi