Patents by Inventor Eun-Joo Jung
Eun-Joo Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11917820Abstract: A method for fabricating semiconductor device includes forming an alternating stack that includes a lower multi-layered stack and an upper multi-layered stack by alternately stacking a dielectric layer and a sacrificial layer over a substrate, forming a vertical trench that divides the upper multi-layered stack into dummy stacks, and forming an asymmetric stepped trench that is extended downward from the vertical trench to divide the lower multi-layered stack into a pad stack and a dummy pad stack, wherein forming the asymmetric stepped trench includes forming a first stepped sidewall that is defined at an edge of the pad stack, and forming a second stepped sidewall that is defined at an edge of the dummy pad stack and occupies less area than the first stepped sidewall.Type: GrantFiled: July 6, 2021Date of Patent: February 27, 2024Assignee: SK hynix Inc.Inventors: Eun-Ho Kim, Eun-Joo Jung, Jong-Hyun Yoo, Ki-Jun Yun, Sung-Hoon Lee
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Publication number: 20240049464Abstract: A method for fabricating semiconductor device includes forming an alternating stack that includes a lower multi-layered stack and an upper multi-layered stack by alternately stacking a dielectric layer and a sacrificial layer over a substrate, forming a vertical trench that divides the upper multi-layered stack into dummy stacks, and forming an asymmetric stepped trench that is extended downward from the vertical trench to divide the lower multi-layered stack into a pad stack and a dummy pad stack, wherein forming the asymmetric stepped trench includes forming a first stepped sidewall that is defined at an edge of the pad stack, and forming a second stepped sidewall that is defined at an edge of the dummy pad stack and occupies less area than the first stepped sidewall.Type: ApplicationFiled: October 17, 2023Publication date: February 8, 2024Inventors: Eun-Ho KIM, Eun-Joo JUNG, Jong-Hyun YOO, Ki-Jun YUN, Sung-Hoon LEE
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Publication number: 20210335800Abstract: A method for fabricating semiconductor device includes forming an alternating stack that includes a lower multi-layered stack and an upper multi-layered stack by alternately stacking a dielectric layer and a sacrificial layer over a substrate, forming a vertical trench that divides the upper multi-layered stack into dummy stacks, and forming an asymmetric stepped trench that is extended downward from the vertical trench to divide the lower multi-layered stack into a pad stack and a dummy pad stack, wherein forming the asymmetric stepped trench includes forming a first stepped sidewall that is defined at an edge of the pad stack, and forming a second stepped sidewall that is defined at an edge of the dummy pad stack and occupies less area than the first stepped sidewall.Type: ApplicationFiled: July 6, 2021Publication date: October 28, 2021Inventors: Eun-Ho KIM, Eun-Joo JUNG, Jong-Hyun YOO, Ki-Jun YUN, Sung-Hoon LEE
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Patent number: 11088160Abstract: A method for fabricating semiconductor device includes forming an alternating stack that includes a lower multi-layered stack and an upper multi-layered stack by alternately stacking a dielectric layer and a sacrificial layer over a substrate, forming a vertical trench that divides the upper multi-layered stack into dummy stacks, and forming an asymmetric stepped trench that is extended downward from the vertical trench to divide the lower multi-layered stack into a pad stack and a dummy pad stack, wherein forming the asymmetric stepped trench includes forming a first stepped sidewall that is defined at an edge of the pad stack, and forming a second stepped sidewall that is defined at an edge of the dummy pad stack and occupies less area than the first stepped sidewall.Type: GrantFiled: September 13, 2019Date of Patent: August 10, 2021Assignee: SK hynix Inc.Inventors: Eun-Ho Kim, Eun-Joo Jung, Jong-Hyun Yoo, Ki-Jun Yun, Sung-Hoon Lee
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Publication number: 20200295028Abstract: A method for fabricating semiconductor device includes forming an alternating stack that includes a lower multi-layered stack and an upper multi-layered stack by alternately stacking a dielectric layer and a sacrificial layer over a substrate, forming a vertical trench that divides the upper multi-layered stack into dummy stacks, and forming an asymmetric stepped trench that is extended downward from the vertical trench to divide the lower multi-layered stack into a pad stack and a dummy pad stack, wherein forming the asymmetric stepped trench includes forming a first stepped sidewall that is defined at an edge of the pad stack, and forming a second stepped sidewall that is defined at an edge of the dummy pad stack and occupies less area than the first stepped sidewall.Type: ApplicationFiled: September 13, 2019Publication date: September 17, 2020Inventors: Eun-Ho KIM, Eun-Joo JUNG, Jong-Hyun YOO, Ki-Jun YUN, Sung-Hoon LEE
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Patent number: 9753228Abstract: An optical transmission and reception connector system includes a cable that has a plug section formed at both ends thereof so as to relay and transmit light and an interfacing module that is mounted on an electronic apparatus and that includes an insertion space into which the plug section is detachably inserted. The cable is provided with a first relay optical path and a second relay optical path.Type: GrantFiled: November 26, 2014Date of Patent: September 5, 2017Assignee: KOREA PHOTONICS TECHNOLOGY INSTITUTEInventors: Sung-Hwan Hwang, Woo-Jin Lee, Myoung-Jin Kim, Eun-Joo Jung, Byung-Sup Rho
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Publication number: 20170045691Abstract: An optical transmission and reception connector system includes a cable that has a plug section formed at both ends thereof so as to relay and transmit light and an interfacing module that is mounted on an electronic apparatus and that includes an insertion space into which the plug section is detachably inserted. The cable is provided with a first relay optical path and a second relay optical path.Type: ApplicationFiled: November 26, 2014Publication date: February 16, 2017Applicant: Korea Photonics Technology InstituteInventors: Sung-Hwan HWANG, Woo-Jin LEE, Myoung-Jin KIM, Eun-Joo JUNG, Byung-Sup RHO
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Patent number: 9293360Abstract: A semiconductor memory device includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer.Type: GrantFiled: June 18, 2014Date of Patent: March 22, 2016Assignee: SK Hynix Inc.Inventors: Jung Il Cho, Jong Moo Choi, Eun Joo Jung
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Patent number: 8936983Abstract: A method of fabricating a semiconductor device according to present invention includes forming a stack layers on a semiconductor substrate having a first area and a second area; forming first gates on the semiconductor substrate of the first area by patterning the stack layers, wherein the first gates are formed a first distance apart from each other; forming a first impurity injection area in the semiconductor substrate of the first area exposed at both sides of each of the first gates; filling a space between the first gates with an insulating layer; forming second gates on the semiconductor substrate of the second area by patterning the stack layers, wherein the second gates are formed a second distance apart from each other, and wherein the second distance is larger than the first distance; and forming a second impurity injection area in the semiconductor device of the second area exposed between the second gates.Type: GrantFiled: December 14, 2011Date of Patent: January 20, 2015Assignee: SK Hynix Inc.Inventors: Kang Jae Lee, Eun Joo Jung
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Publication number: 20140295641Abstract: A semiconductor memory device includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer.Type: ApplicationFiled: June 18, 2014Publication date: October 2, 2014Inventors: Jung Il CHO, Jong Moo CHOI, Eun Joo JUNG
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Publication number: 20140151779Abstract: A semiconductor memory device includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer.Type: ApplicationFiled: February 28, 2013Publication date: June 5, 2014Applicant: SK HYNIX INC.Inventors: Jung Il CHO, Jong Moo CHOI, Eun Joo JUNG
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Patent number: 8400640Abstract: Provided is an optical sensor interrogation system. The optical sensor interrogation system includes: a light source unit which matches round-trip time of light and wavelength tunable cycle time of light in a resonator and emits light; a sensing unit which receives an optical signal in which a center wavelength periodically tunes, from the light source unit and tunes the center wavelength of the optical signal according to physical changes applied from the outside; and a signal processing unit which receives the optical signal reflected from the sensing unit, detects data, and images the data. In particular, the light source unit includes a delaying unit which delays the round-trip time of light and a tunable filter which tunes the wavelength of light so as to match the round-trip time of light with the wavelength tunable cycle time of light.Type: GrantFiled: September 24, 2009Date of Patent: March 19, 2013Assignee: Pusan National University Industry-University Cooperation FoundationInventors: Chang-Seok Kim, Myung-Yung Jeong, Jae-Seok Park, Eun-Joo Jung, Hyung-Seok Lee
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Publication number: 20120156841Abstract: A method of fabricating a semiconductor device according to present invention includes forming a stack layers on a semiconductor substrate having a first area and a second area; forming first gates on the semiconductor substrate of the first area by patterning the stack layers, wherein the first gates are formed a first distance apart from each other; forming a first impurity injection area in the semiconductor substrate of the first area exposed at both sides of each of the first gates; filling a space between the first gates with an insulating layer; forming second gates on the semiconductor substrate of the second area by patterning the stack layers, wherein the second gates are formed a second distance apart from each other, and wherein the second distance is larger than the first distance; and forming a second impurity injection area in the semiconductor device of the second area exposed between the second gates.Type: ApplicationFiled: December 14, 2011Publication date: June 21, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Kang Jae LEE, Eun Joo JUNG
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Publication number: 20100103426Abstract: Provided is an optical sensor interrogation system. The optical sensor interrogation system includes: a light source unit which matches round-trip time of light and wavelength tunable cycle time of light in a resonator and emits light; a sensing unit which receives an optical signal in which a center wavelength periodically tunes, from the light source unit and tunes the center wavelength of the optical signal according to physical changes applied from the outside; and a signal processing unit which receives the optical signal reflected from the sensing unit, detects data, and images the data. In particular, the light source unit includes a delaying unit which delays the round-trip time of light and a tunable filter which tunes the wavelength of light so as to match the round-trip time of light with the wavelength tunable cycle time of light.Type: ApplicationFiled: September 24, 2009Publication date: April 29, 2010Inventors: Chang-Seok Kim, Myung-Yung Jeong, Jae-Seok Park, Eun-Joo Jung, Hyung-Seok Lee