Abstract: A chip stack is provided and includes two or more chips, a solder joint operably disposed between adjacent ones of the two or more chips, the solder joint occupying about 25-30% or more of an area of the chip stack and insulating walls disposed on at least one of the two or more chips to separate the solder joint from an adjacent solder joint.

Abstract: Methods and structures are provided for packaging identically processed chips in a stacked structure. A latch chain includes a first latch chain, having a single or multiple latches, associated with a first chip. The first latch chain is structured to read data information from the first chip. The latch chain includes a second latch chain, having a single or multiple latches, associated with a second chip. The second latch chain is structured to read data information from the second chip. The first latch chain and the second latch chain are connected to one another such that form a single latch chain that crosses chip boundaries. The first latch chain and the second latch chain are structured to provide identification information for identifying the first chip and the second chip, respectively.

Abstract: A method of forming a chip stack is provided and includes arraying solder pads along a plane of a major surface of a substrate forming walls of electrically insulating material between adjacent ones of the solder pads.

Abstract: Cooled electronic assemblies and methods of fabrication are provided. In one embodiment, the assembly includes a coolant-cooled electronic module with one or more electronic component(s), and one or more coolant-carrying channel(s) integrated within the module, and configured to facilitate flow of coolant through the module for cooling the electronic component(s). In addition, the assembly includes a coolant manifold structure detachably coupled to the electronic module. The manifold structure facilitates flow of coolant to the coolant-carrying channel(s) of the electronic module, and the coolant manifold structure and electronic module include adjoining surfaces. One surface of the adjoining surfaces includes a plurality of coolant capillaries or passages. The coolant capillaries are sized to inhibit, for instance, via surface tension, leaking of coolant therefrom at the one surface with decoupling of the coolant manifold structure and electronic module along the adjoining surfaces.

Abstract: A composite wiring circuit with electrical through connections and method of manufacturing the same. The composite wiring circuit includes a glass with first electrically-conducting through vias. The first electrically-conducting through vias pass from a top surface of the glass layer to a bottom surface of the glass layer. The composite wiring circuit further includes an interposer layer with second electrically-conducting through vias. The second electrically-conducting through vias pass from a top surface of the interposer layer to a bottom surface of the interposer layer. The second electrically-conducting through vias are electrically coupled to the first electrically-conducting through vias.

Abstract: Nanochannel sensors and methods for constructing nanochannel sensors. An example method includes forming a sacrificial line on an insulating layer, forming a dielectric layer, etching a pair of electrode trenches, forming a pair of electrodes, and removing the sacrificial line to form a nanochannel. The dielectric layer may be formed on insulating layer and around the sacrificial line. The pair of electrode trenches may be etched in the dielectric layer on opposite sides of the sacrificial line. The pair of electrodes may be formed by filling the electrode trenches with electrode material. The sacrificial line may be removed by forming a nanochannel between the at least one pair of electrodes.

Abstract: A method of forming a chip stack is provided and includes arraying solder pads along a plane of a major surface of a substrate forming walls of electrically insulating material between adjacent ones of the solder pads.

Abstract: Node interconnect architectures to implement a high performance supercomputer are provided. For example, a node interconnect architecture for connecting a multitude of nodes (or processors) of a supercomputer is implemented using an all-to-all electrical and optical connection network which provides two independent communication paths between any two processors of the supercomputer, wherein a communication path includes at most two electrical links and one optical link.

Abstract: Node Interconnect architectures to implement a high performance supercomputer are provided. For example, a node interconnect architecture for connecting a multitude of nodes (or processors) of a supercomputer is implemented using an all-to-all electrical and optical connection network which provides two independent communication paths between any two processors of the supercomputer, wherein a communication path includes at most two electrical links and one optical link.

Abstract: The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod to the linear groove, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. Another method includes forming an alignment ridge on an alignment rail, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail.

Abstract: Cooled electronic assemblies, and a method of decoupling a cooled electronic assembly, are provided. In one embodiment, the assembly includes a coolant-cooled electronic module with one or more electronic components and one or more coolant-carrying channels integrated within the module and configured to facilitate flow of coolant through the module for cooling the electronic component(s). In addition, the assembly includes a coolant manifold structure detachably coupled to the electronic module. The manifold structure, which includes a coolant inlet and outlet in fluid communication with the coolant-carrying channel(s) of the electronic module, facilitates flow of coolant through the coolant-carrying channel, and thus cooling of the electronic component(s). Coolant-absorbent material is positioned at the interface between the electronic module and the manifold structure to facilitate absorbing any excess coolant during a stepwise detaching of the manifold structure from the electronic module.

Abstract: A method of assembling a packaging structure is provided and includes directly electrically interconnecting respective active surfaces of first and second chips in a face-to-face arrangement, electrically interconnecting at least one of the respective sidewalls of the first and second chips to a common chip and orienting the respective active surfaces of the first and second chips transversely with respect to the common chip.

Abstract: A packaging structure is provided. The packaging structure includes first and second chips, at least one surface of each of the first and second chips being an active surface and a common chip to which at least one of the first and second chips is electrically interconnected. The respective active surfaces of the first and second chips are directly electrically interconnected to one another in a face-to-face arrangement and are oriented transversely with respect to the common chip.

Abstract: Nanochannel sensors and methods for constructing nanochannel sensors. An example method includes forming a sacrificial line on an insulating layer, forming a dielectric layer, etching a pair of electrode trenches, forming a pair of electrodes, and removing the sacrificial line to form a nanochannel. The dielectric layer may be formed on insulating layer and around the sacrificial line. The pair of electrode trenches may be etched in the dielectric layer on opposite sides of the sacrificial line. The pair of electrodes may be formed by filling the electrode trenches with electrode material. The sacrificial line may be removed by forming a nanochannel between the at least one pair of electrodes.

Abstract: Nanochannel sensors and methods for constructing nanochannel sensors. An example method includes forming a sacrificial line on an insulating layer, forming a dielectric layer, etching a pair of electrode trenches, forming a pair of electrodes, and removing the sacrificial line to form a nanochannel. The dielectric layer may be formed on insulating layer and around the sacrificial line. The pair of electrode trenches may be etched in the dielectric layer on opposite sides of the sacrificial line. The pair of electrodes may be formed by filling the electrode trenches with electrode material. The sacrificial line may be removed by forming a nanochannel between the at least one pair of electrodes.

Abstract: Nanochannel sensors and methods for constructing nanochannel sensors. An example method includes forming a sacrificial line on an insulating layer, forming a dielectric layer, etching a pair of electrode trenches, forming a pair of electrodes, and removing the sacrificial line to form a nanochannel. The dielectric layer may be formed on insulating layer and around the sacrificial line. The pair of electrode trenches may be etched in the dielectric layer on opposite sides of the sacrificial line. The pair of electrodes may be formed by filling the electrode trenches with electrode material. The sacrificial line may be removed by forming a nanochannel between the at least one pair of electrodes.

Abstract: Embodiments of the invention comprise a homogeneous heat spreading cap element in chip packages to facilitate better heat spreading and dissipation. The heat spreading cap comprises a single high-K graphite layer supported by a copper frame for increased stability and reduced thermal warpage during handling and operation while minimizing thermal penalty by reducing the amount of material having a relatively low heat conductivity that is needed in conventional heat spreading caps.

Abstract: A chip packaging apparatus includes a substrate, a load frame attached to the substrate by an adhesive material, the load frame being formed to define an aperture and a semiconductor chip mounted on the substrate within the aperture. A thickness of the adhesive material between the load frame and the substrate is varied and adjusted such that a surface of the load frame opposite the substrate is disposed substantially in parallel to a surface of the chip opposite the substrate.

Abstract: A method of forming a chip stack is provided and includes arraying solder pads along a plane of a major surface of a substrate forming walls of electrically insulating material between adjacent ones of the solder pads.

Abstract: A chip stack is provided and includes two or more chips, a solder joint operably disposed between adjacent ones of the two or more chips, the solder joint occupying about 25-30% or more of an area of the chip stack and insulating walls disposed on at least one of the two or more chips to separate the solder joint from an adjacent solder joint.