Patents by Inventor Evanthia Papadopoulou
Evanthia Papadopoulou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7810060Abstract: Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes the critical area for composite fault mechanisms of the integrated circuit design based on the composite Voronoi diagram.Type: GrantFiled: June 4, 2008Date of Patent: October 5, 2010Assignee: International Business Machines CorporationInventors: Robert J. Allen, Jr., Evanthia Papadopoulou, Mervyn Yee-Min Tan
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Patent number: 7752580Abstract: Disclosed herein are embodiments of a system and an associated method for analyzing an integrated circuit to determine the value of a particular attribute (i.e., a physical or electrical property) in that integrated circuit. In the embodiments, an open deterministic sequencing technique is used to select a sequence of points representing centers of sample windows in an integrated circuit layout. Then, the value of the particular attribute is determined for each sample window and the results are accumulated in order to infer an overall value for that particular attribute for the entire integrated circuit layout. This sequencing technique has the advantage of allowing additional sample windows to be added and/or the sizes and shapes of the windows to be varied without hindering the quality of the sample.Type: GrantFiled: July 26, 2007Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Sarah C. Braasch, Jason D. Hibbeler, Rouwaida N. Kanj, Daniel N. Maynard, Sani R. Nassif, Evanthia Papadopoulou
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Patent number: 7752589Abstract: A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern.Type: GrantFiled: January 5, 2007Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Robert J. Allen, Sarah C. Braasch, Matthew T. Guzowski, Jason D. Hibbeler, Daniel N. Maynard, Kevin W. McCullen, Evanthia Papadopoulou, Mervyn Y. Tan, Robert F. Walker
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Patent number: 7703061Abstract: A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.Type: GrantFiled: August 6, 2008Date of Patent: April 20, 2010Assignee: International Business Machines CorporationInventors: Evanthia Papadopoulou, Daniel N. Maynard
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Patent number: 7685553Abstract: An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.Type: GrantFiled: April 11, 2007Date of Patent: March 23, 2010Assignee: International Business Machines CorporationInventors: Evanthia Papadopoulou, Ruchir Puri, Mervyn Y. Tan, Louise H. Trevillyan, Hua Xiang
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Patent number: 7661080Abstract: In one embodiment, the present invention is a method and apparatus for net-aware critical area extraction. One embodiment of the inventive method for determining the critical area of an integrated circuit includes modeling a net corresponding to the integrated circuit as a graph, where the net is made up of a plurality of interconnected shapes spanning one or more layers of the integrated circuit. All generators for opens are then defined and identified. The Voronoi diagram of the identified generators is computed, and the critical area is computed in accordance with the Voronoi diagram.Type: GrantFiled: January 24, 2007Date of Patent: February 9, 2010Assignee: International Business Machines CorporationInventors: Evanthia Papadopoulou, Sarah Braasch, Mervyn Y. Tan
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Patent number: 7577927Abstract: A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.Type: GrantFiled: August 6, 2008Date of Patent: August 18, 2009Assignee: International Business Machines CorporationInventors: Evanthia Papadopoulou, Daniel N. Maynard
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Patent number: 7555735Abstract: A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.Type: GrantFiled: October 29, 2007Date of Patent: June 30, 2009Assignee: International Business Machines CorporationInventors: Evanthia Papadopoulou, Daniel N. Maynard
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Publication number: 20090125852Abstract: In one embodiment, the present invention is a method and apparatus for net-aware critical area extraction. One embodiment of the inventive method for determining the critical area of an integrated circuit includes modeling a net corresponding to the integrated circuit as a graph, the net comprising a plurality of interconnected shapes spanning one or more layers of the integrated circuit, identifying one or more core elements in the graph, the core elements including bridges, articulation points, and biconnected components, computing a first Voronoi diagram for a core portion of the graph on a selected layer, including the core elements, emphasizing regions in the first Voronoi diagram where a critical radius is known, computing a second, higher-order Voronoi diagram in accordance with the emphasized regions, and computing the critical area in accordance with the higher-order Voronoi diagram.Type: ApplicationFiled: November 9, 2007Publication date: May 14, 2009Inventor: EVANTHIA PAPADOPOULOU
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Publication number: 20090031265Abstract: A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.Type: ApplicationFiled: August 6, 2008Publication date: January 29, 2009Inventors: Evanthia Papadopoulou, Daniel N. Maynard
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Publication number: 20090031263Abstract: Disclosed herein are embodiments of a system and an associated method for analyzing an integrated circuit to determine the value of a particular attribute (i.e., a physical or electrical property) in that integrated circuit. In the embodiments, an open deterministic sequencing technique is used to select a sequence of points representing centers of sample windows in an integrated circuit layout. Then, the value of the particular attribute is determined for each sample window and the results are accumulated in order to infer an overall value for that particular attribute for the entire integrated circuit layout. This sequencing technique has the advantage of allowing additional sample windows to be added and/or the sizes and shapes of the windows to be varied without hindering the quality of the sample.Type: ApplicationFiled: July 26, 2007Publication date: January 29, 2009Inventors: Sarah C. Braasch, Jason D. Hibbeler, Rouwaida N. Kanj, Daniel N. Maynard, Sani R. Nassif, Evanthia Papadopoulou
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Publication number: 20090031266Abstract: A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.Type: ApplicationFiled: August 6, 2008Publication date: January 29, 2009Inventors: Evanthia Papadopoulou, Daniel N. Maynard
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Publication number: 20080256502Abstract: An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.Type: ApplicationFiled: April 11, 2007Publication date: October 16, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Evanthia Papadopoulou, Ruchir Puri, Mervyn Y. Tan, Louise H. Trevillyan, Hua Xiang
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Publication number: 20080235641Abstract: Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes the critical area for composite fault mechanisms of the integrated circuit design based on the composite Voronoi diagram.Type: ApplicationFiled: June 4, 2008Publication date: September 25, 2008Applicant: International Business Machines CorporationInventors: Robert J. Allen, Evanthia Papadopoulou, Mervyn Yee-Min Tan
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Publication number: 20080178137Abstract: In one embodiment, the present invention is a method and apparatus for net-aware critical area extraction. One embodiment of the inventive method for determining the critical area of an integrated circuit includes modeling a net corresponding to the integrated circuit as a graph, where the net is made up of a plurality of interconnected shapes spanning one or more layers of the integrated circuit. All generators for opens are then defined and identified. The Voronoi diagram of the identified generators is computed, and the critical area is computed in accordance with the Voronoi diagram.Type: ApplicationFiled: January 24, 2007Publication date: July 24, 2008Inventors: Evanthia Papadopoulou, Sarah Braasch, Mervyn Y. Tan
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Patent number: 7404164Abstract: A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.Type: GrantFiled: February 4, 2004Date of Patent: July 22, 2008Assignee: International Business Machines CorporationInventors: Evanthia Papadopoulou, Daniel N. Maynard
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Patent number: 7404159Abstract: Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes the critical area for composite fault mechanisms of the integrated circuit design based on the composite Voronoi diagram.Type: GrantFiled: October 5, 2006Date of Patent: July 22, 2008Assignee: International Business Machines CorporationInventors: Robert J. Allen, Evanthia Papadopoulou, Mervyn Yee-Min Tan
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Publication number: 20080168414Abstract: A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern.Type: ApplicationFiled: January 5, 2007Publication date: July 10, 2008Inventors: Robert J. Allen, Sarah C. Braasch, Matthew T. Guzowski, Jason D. Hibbeler, Daniel N. Maynard, Kevin W. McCullen, Evanthia Papadopoulou, Mervyn Y. Tan, Robert F. Walker
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Publication number: 20080059929Abstract: A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.Type: ApplicationFiled: October 29, 2007Publication date: March 6, 2008Inventors: Evanthia Papadopoulou, Daniel Maynard
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Publication number: 20070256040Abstract: Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes the critical area for composite fault mechanisms of the integrated circuit design based on the composite Voronoi diagram.Type: ApplicationFiled: October 5, 2006Publication date: November 1, 2007Inventors: Robert Allen, Evanthia Papadopoulou, Mervyn Tan