Abstract: Method, system and program product for determining a critical area in a region of an integrated circuit layout using Voronoi diagrams and shape biasing. The method includes the steps of generating a biased Voronoi diagram based on a layout geometry of the region and incorporating a shape bias; and determining the critical area for the region using the biased Voronoi diagram.

Abstract: Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes the critical area for composite fault mechanisms of the integrated circuit design based on the composite Voronoi diagram.

Abstract: Method, system and program product for determining a critical area in a region of an integrated circuit layout using Voronoi diagrams and shape biasing. The method includes the steps of generating a biased Voronoi diagram based on a layout geometry of the region and incorporating a shape bias; and determining the critical area for the region using the biased Voronoi diagram.

Abstract: Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes the critical area for composite fault mechanisms of the integrated circuit design based on the composite Voronoi diagram.

Abstract: A method of creating a photomask layout for projecting an image of an integrated circuit design comprises creating a layout of spaced integrated circuit shapes to be projected via the photomask, determining bisectors between adjacent ones of the spaced integrated circuit shapes, and creating sub-resolution assist features along at least some of the bisectors between the adjacent ones of the spaced integrated circuit shapes. The bisectors may be determined by creating Voronoi cells around the spaced integrated circuit shapes. Preferably, the adjacent ones of the spaced integrated circuit shapes are parallel to each other and the sub-resolution assist features along the bisectors are parallel to the spaced integrated circuit shapes.

Abstract: A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.

Abstract: A method for computing critical area for opens of a layout, which may be implemented by program storage device readable by machine, tangibly embodying a program of instructions executable by the machine, to perform the method steps includes computing Voronoi diagrams of shapes of the layout, determining core elements and weights for the core elements of the shapes, computing a weighted Voronoi diagram for the layout to arrive at a partitioning of the layout into regions, computing critical area within each region and summing the critical areas to arrive at a total critical area for opens in the layout.

Abstract: An efficient computer implemented method computes critical area for via blocks in Very Large Scale Integrated (VLSI) circuits. The method is incremental and takes advantage of the hierarchy in the design. In order to increase the efficiency further we use the L∞ or the L1 metric instead of the Euclidean geometry.

Abstract: A method for computing critical area for shorts of a layout, in accordance with the present invention, includes the steps of computing a Voronoi diagram for the layout, computing a second order Voronoi diagram to arrive at a partitioning of the layout into regions, computing critical area within each region and summing the critical areas to arrive at a total critical area for shorts in the layout. A system is also provided for calculating the critical area.

Abstract: An efficient method to compute critical area for shorts and breaks in rectilinear layouts in Very Large Scale Integrated (VLSI) circuits. The method is incremental and works in the L.sub..infin. geometry and has three major steps: Compute critical area for rectilinear layouts for both extra material and missing material defects (i.e., shorts and opens) by modeling defects as squares (which corresponds to the L.sub..infin. metric) instead of circles (Euclidean geometry). Treat the critical region for shorts and opens between any two edges or corners of the layout as a rectangle that grows uniformly as the defect radius increases. This is valid for rectilinear layouts and square defects (L.sub..infin. metric) . Use an incremental critical area algorithm for shorts and opens, which are computed for rectilinear layouts assuming square defects. Non-rectilinear layouts are approximated, first, by a rectilinear layout using a shape processing tool.