Patents by Inventor Evelyn Napetschnig

Evelyn Napetschnig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11069644
    Abstract: A semiconductor device and method is disclosed. In one embodiment, the semiconductor device comprises a semiconductor die comprising a first surface and a second surface opposite to the first surface, a first metallization layer disposed on the first surface of the semiconductor die, a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, and a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body, wherein the first contact member is connected with the Ni-based layer to the first solder layer.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: July 20, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thomas Behrens, Alexander Heinrich, Evelyn Napetschnig, Bernhard Weidgans, Catharina Wille, Christina Yeong
  • Publication number: 20210167034
    Abstract: A chip arrangement including: a chip including a chip back side; a substrate including a surface with a plating; and a zinc-based solder alloy which attaches the chip back side to the plating on the surface of the substrate, the zinc-based solder alloy including, by weight, 1% to 30% aluminum, 0.5% to 20% germanium, and 0.5% to 20% gallium, wherein a balance of the zinc-based solder alloy is zinc.
    Type: Application
    Filed: January 15, 2021
    Publication date: June 3, 2021
    Inventors: Manfred MENGEL, Alexander HEINRICH, Steffen ORSO, Thomas BEHRENS, Oliver EICHINGER, Lim FONG, Evelyn NAPETSCHNIG, Edmund RIEDL
  • Publication number: 20210091025
    Abstract: A semiconductor substrate has a bond pad. The bond pad includes a layer of an aluminum alloy having a chemical composition including at least 0.3% by weight of at least one of Zn, Mg, Sc, Zr, Ti, Ag and/or Mn, with the balance being at least Al and incidental impurities.
    Type: Application
    Filed: September 17, 2020
    Publication date: March 25, 2021
    Inventors: Gert Pfahl, Daniel Bolowski, Marian Sebastian Broll, Michael Kreuz, Evelyn Napetschnig, Holger Schulze, Stefan Woehlert
  • Patent number: 10930614
    Abstract: A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: February 23, 2021
    Assignee: Infineon Technologies AG
    Inventors: Manfred Mengel, Alexander Heinrich, Steffen Orso, Thomas Behrens, Oliver Eichinger, Lim Fong, Evelyn Napetschnig, Edmund Riedl
  • Patent number: 10914018
    Abstract: A semiconductor package includes a plurality of metal leads and a semiconductor die attached to the plurality of metal leads by an interconnect. A surface of the plurality of metal leads, a metallized surface of the semiconductor die, and/or a surface of the interconnect comprises Cu and has a thermal conductivity in a range of 340 to 400 W/mK and an electrical conductivity in a range of 80 to 110% IACS. One or more of the surfaces which comprise Cu and have a thermal conductivity in the range of 340 to 400 W/mK and an electrical conductivity in the range of 80 to 110% IACS also includes micropores having a diameter in a range of 1 ?m to 10 ?m. A method of manufacturing a metal surface with such micropores also is described.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: February 9, 2021
    Assignee: Infineon Technologies AG
    Inventors: Norbert Pielmeier, Chin Yung Lai, Swee Kah Lee, Muhammad Muhammat Sanusi, Evelyn Napetschnig, Nurfarena Othman, Siew Ching Seah
  • Publication number: 20200343094
    Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.
    Type: Application
    Filed: July 10, 2020
    Publication date: October 29, 2020
    Applicant: Infineon Technologies AG
    Inventors: Paul Frank, Gretchen Adema, Thomas Bertaud, Michael Ehmann, Eric Graetz, Kamil Karlovsky, Evelyn Napetschnig, Werner Robl, Tobias Schmidt, Joachim Seifert, Frank Wagner, Stefan Woehlert
  • Publication number: 20200291538
    Abstract: A semiconductor package includes a plurality of metal leads and a semiconductor die attached to the plurality of metal leads by an interconnect. A surface of the plurality of metal leads, a metallized surface of the semiconductor die, and/or a surface of the interconnect comprises Cu and has a thermal conductivity in a range of 340 to 400 W/mK and an electrical conductivity in a range of 80 to 110% IACS. One or more of the surfaces which comprise Cu and have a thermal conductivity in the range of 340 to 400 W/mK and an electrical conductivity in the range of 80 to 110% IACS also includes micropores having a diameter in a range of 1 ?m to 10 ?m. A method of manufacturing a metal surface with such micropores also is described.
    Type: Application
    Filed: March 12, 2019
    Publication date: September 17, 2020
    Inventors: Norbert Pielmeier, Chin Yung Lai, Swee Kah Lee, Muhammad Muhammat Sanusi, Evelyn Napetschnig, Nurfarena Othman, Siew Ching Seah
  • Patent number: 10741402
    Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: August 11, 2020
    Assignee: Infineon Technologies AG
    Inventors: Paul Frank, Gretchen Adema, Thomas Bertaud, Michael Ehmann, Eric Graetz, Kamil Karlovsky, Evelyn Napetschnig, Werner Robl, Tobias Schmidt, Joachim Seifert, Frank Wagner, Stefan Woehlert
  • Publication number: 20200105704
    Abstract: A semiconductor device and method is disclosed. In one embodiment, the semiconductor device comprises a semiconductor die comprising a first surface and a second surface opposite to the first surface, a first metallization layer disposed on the first surface of the semiconductor die, a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, and a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body, wherein the first contact member is connected with the Ni-based layer to the first solder layer.
    Type: Application
    Filed: August 30, 2019
    Publication date: April 2, 2020
    Applicant: Infineon Technologies AG
    Inventors: Thomas Behrens, Alexander Heinrich, Evelyn Napetschnig, Bernhard Weidgans, Catharina Wille, Christina Yeong
  • Patent number: 10573611
    Abstract: A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: February 25, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Kamil Karlovsky, Evelyn Napetschnig, Michael Ehmann, Mark James Harrison, Anton Pugatschow
  • Publication number: 20200043876
    Abstract: A package includes an electronic chip having a pad. The pad is at least partially covered with adhesion enhancing structures. The pad and the adhesion enhancing structures have at least aluminium in common.
    Type: Application
    Filed: July 24, 2019
    Publication date: February 6, 2020
    Inventors: Evelyn Napetschnig, Wei Cheat Lee, Wei Lee Lim, Frank Renner, Michael Rogalli
  • Publication number: 20190148233
    Abstract: A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.
    Type: Application
    Filed: January 15, 2019
    Publication date: May 16, 2019
    Inventors: Karl Mayer, Evelyn Napetschnig, Michael Pinczolits, Michael Sternad, Michael Roesner
  • Patent number: 10276362
    Abstract: According to various embodiments, a method for processing a semiconductor region, wherein the semiconductor region comprises at least one precipitate, may include: forming a precipitate removal layer over the semiconductor region, wherein the precipitate removal layer may define an absorption temperature at which a chemical solubility of a constituent of the at least one precipitate is greater in the precipitate removal layer than in the semiconductor region; and heating the at least one precipitate above the absorption temperature.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: April 30, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Evelyn Napetschnig, Sandra Wirtitsch, Mario Barusic, Aleksander Hinz, Robert Hartl, Georg Schinner
  • Patent number: 10262959
    Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: April 16, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Evelyn Napetschnig, Ulrike Fastner, Alexander Heinrich, Thomas Fischer
  • Publication number: 20190051624
    Abstract: A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer.
    Type: Application
    Filed: October 17, 2018
    Publication date: February 14, 2019
    Inventors: Kamil Karlovsky, Evelyn Napetschnig, Michael Ehmann, Mark James Harrison, Anton Pugatschow
  • Patent number: 10186458
    Abstract: A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: January 22, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Karl Mayer, Evelyn Napetschnig, Michael Pinczolits, Michael Sternad, Michael Roesner
  • Publication number: 20180366427
    Abstract: A method of forming an aluminum oxide layer is provided. The method includes providing a metal surface including at least one metal of a group of metals, the group of metals consisting of copper, aluminum, palladium, nickel, silver, and alloys thereof. The method further includes depositing an aluminum oxide layer on the metal surface by atomic layer deposition, wherein a maximum processing temperature during the depositing is 280° C., such that the aluminum oxide layer is formed with a surface having a liquid solder contact angle of less than 40°.
    Type: Application
    Filed: June 19, 2018
    Publication date: December 20, 2018
    Inventors: Michael Rogalli, Johann Gatterbauer, Wolfgang Lehnert, Kurt Matoy, Evelyn Napetschnig, Manfred Schneegans, Bernhard Weidgans
  • Patent number: 10115688
    Abstract: A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: October 30, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Kamil Karlovsky, Evelyn Napetschnig, Michael Ehmann, Mark Harrison, Anton Pugatschow
  • Publication number: 20180082848
    Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.
    Type: Application
    Filed: August 31, 2017
    Publication date: March 22, 2018
    Applicant: Infineon Technologies AG
    Inventors: Paul Frank, Gretchen Adema, Thomas Bertaud, Michael Ehmann, Eric Graetz, Kamil Karlovsky, Evelyn Napetschnig, Werner Robl, Tobias Schmidt, Joachim Seifert, Frank Wagner, Stefan Woehlert
  • Publication number: 20170323865
    Abstract: A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer.
    Type: Application
    Filed: July 26, 2017
    Publication date: November 9, 2017
    Inventors: Manfred MENGEL, Alexander HEINRICH, Steffen ORSO, Thomas BEHRENS, Oliver EICHINGER, Lim FONG, Evelyn NAPETSCHNIG, Edmund RIEDL