Patents by Inventor Evelyn Napetschnig

Evelyn Napetschnig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor devices and methods of forming thereof
    Patent number: 9484316
    Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: November 1, 2016
    Assignee: Infineon Technologies AG
    Inventors: Evelyn Napetschnig, Ulrike Fastner, Alexander Heinrich, Thomas Fischer
  • Method for Processing a Semiconductor Workpiece and Semiconductor Workpiece
    Publication number: 20150325535
    Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization layer over a semiconductor workpiece; patterning the first metallization layer; and depositing a second metallization layer over the patterned first metallization layer, wherein depositing the second metallization layer includes an electroless deposition process including immersing the patterned first metallization layer in a metal electrolyte.
    Type: Application
    Filed: May 8, 2014
    Publication date: November 12, 2015
    Applicant: Infineon Technologies AG
    Inventors: Stephan HENNECK, Evelyn NAPETSCHNIG, Daniel PEDONE, Bernhard WEIDGANS, Simon FAISS, Ivan NIKITIN
  • LAYER STACKS AND INTEGRATED CIRCUIT ARRANGEMENTS
    Publication number: 20150228607
    Abstract: In various embodiments, a layer stack is provided. The layer stack may include a carrier; a first metal disposed over the carrier; a second metal disposed over the first metal; and a solder material disposed above the second metal or a material that provides contact to a solder that is supplied by an external source. The second metal may have a melting temperature of at least 1800° C. and is not or substantially not dissolved in the solder material at least one of during a soldering process and after the soldering process.
    Type: Application
    Filed: April 22, 2015
    Publication date: August 13, 2015
    Inventors: Tobias Schmidt, Evelyn Napetschnig, Franz Stueckler, Anton Pugatschow, Mark Harrison
  • Semiconductor Devices and Methods of Forming Thereof
    Publication number: 20150123264
    Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.
    Type: Application
    Filed: November 1, 2013
    Publication date: May 7, 2015
    Inventors: Evelyn Napetschnig, Ulrike Fastner, Alexander Heinrich, Thomas Fischer
  • Backside processing of semiconductor devices
    Patent number: 8866299
    Abstract: A semiconductor device includes a workpiece having a bottom surface opposite the top surface. Metallization layers are disposed over the top surface and a protective layer is disposed over the metallization layers. The semiconductor device further includes a metal silicide layer disposed on the bottom surface. The metal silicide layer is less than about five atomic layers in thickness. A first metal layer is disposed over the metal silicide layer such that a metal of the first metal layer is the same as a metal of the metal silicide layer.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies AG
    Inventors: Mark Harrison, Evelyn Napetschnig, Franz Stueckler
  • Backside Processing of Semiconductor Devices
    Publication number: 20140015141
    Abstract: A semiconductor device includes a workpiece having a bottom surface opposite the top surface. Metallization layers are disposed over the top surface and a protective layer is disposed over the metallization layers. The semiconductor device further includes a metal silicide layer disposed on the bottom surface. The metal silicide layer is less than about five atomic layers in thickness. A first metal layer is disposed over the metal silicide layer such that a metal of the first metal layer is the same as a metal of the metal silicide layer.
    Type: Application
    Filed: July 1, 2013
    Publication date: January 16, 2014
    Applicant: Infineon Technoloiges AG
    Inventors: Mark Harrison, Evelyn Napetschnig, Franz Stueckler
  • Component and Method of Manufacturing a Component Using an Ultrathin Carrier
    Publication number: 20140008805
    Abstract: A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.
    Type: Application
    Filed: July 5, 2012
    Publication date: January 9, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Karl Mayer, Evelyn Napetschnig, Michael Pinczolits, Michael Sternad, Michael Roesner
  • Backside processing of semiconductor devices
    Patent number: 8487440
    Abstract: A semiconductor device includes a workpiece having a bottom surface opposite the top surface. Metallization layers are disposed over the top surface and a protective layer is disposed over the metallization layers. The semiconductor device further includes a metal silicide layer disposed on the bottom surface. The metal silicide layer is less than about five atomic layers in thickness. A first metal layer is disposed over the metal silicide layer such that a metal of the first metal layer is the same as a metal of the metal silicide layer.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: July 16, 2013
    Assignee: Infineon Technologies AG
    Inventors: Mark Harrison, Evelyn Napetschnig, Franz Stueckler
  • SOLDER ALLOYS AND ARRANGEMENTS
    Publication number: 20120313230
    Abstract: A solder alloy is providing, the solder alloy including zinc, aluminum, magnesium and gallium, wherein the aluminum constitutes by weight 8% to 20% of the alloy, the magnesium constitutes by weight 0.5% to 20% of the alloy and the gallium constitutes by weight 0.5% to 20% of the alloy, the rest of the alloy including zinc.
    Type: Application
    Filed: June 7, 2011
    Publication date: December 13, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Manfred MENGEL, Alexander HEINRICH, Steffen ORSO, Thomas BEHRENS, Oliver EICHINGER, Lim FONG, Evelyn NAPETSCHNIG, Edmund RIEDL
  • LAYER STACKS AND INTEGRATED CIRCUIT ARRANGEMENTS
    Publication number: 20120068345
    Abstract: In various embodiments, a layer stack is provided. The layer stack may include a carrier; a first metal disposed over the carrier; a second metal disposed over the first metal; and a solder material disposed above the second metal or a material that provides contact to a solder that is supplied by an external source. The second metal may have a melting temperature of at least 1800° C. and is not or substantially not dissolved in the solder material at least one of during a soldering process and after the soldering process.
    Type: Application
    Filed: September 16, 2010
    Publication date: March 22, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Tobias Schmidt, Evelyn Napetschnig, Franz Stueckler, Anton Pugatschow
  • Backside Processing of Semiconductor Devices
    Publication number: 20120007244
    Abstract: A semiconductor device includes a workpiece having a bottom surface opposite the top surface. Metallization layers are disposed over the top surface and a protective layer is disposed over the metallization layers. The semiconductor device further includes a metal silicide layer disposed on the bottom surface. The metal silicide layer is less than about five atomic layers in thickness. A first metal layer is disposed over the metal silicide layer such that a metal of the first metal layer is the same as a metal of the metal silicide layer.
    Type: Application
    Filed: July 9, 2010
    Publication date: January 12, 2012
    Inventors: Mark Harrison, Evelyn Napetschnig, Franz Stueckler