Abstract: A single-channel, single-poly floating gate (EEPROM-type) memristor including asymmetric source/drain-to-gate coupling and an asymmetric channel doping pattern. Asymmetric source/drain-to-gate coupling is achieved by configuring the drain, source and floating gate such that the gate-to-drain capacitance is greater than the gate-to-source capacitance. The asymmetric channel doping pattern is implemented by forming different drain-side and source-side doping portions (i.e., different N-type or P-type implant configurations and/or positions). The asymmetric channel doping pattern is preferably formed using standard CMOS implants (e.g., NLDD and P-type pocket implants). Multiple N-type and P-type implants may be selectively positioned to achieve a desired balance between program/erase speeds, reverse (read direction) threshold voltage and immunity to read-disturb and over-erase. A drain-side diode may be additionally used to suppress over-erase.

Abstract: A method for radiation dosage measurement includes: (1) exposing a plurality of single-poly floating gate sensor cells to radiation; (2) measuring threshold voltage differences between logical pairs of the exposed sensor cells using differential read operations, wherein the sensor cells of each logical pair are separated by a distance large enough that radiation impinging on one of the sensor cells does not influence the other sensor cell; (3) determining whether each logical pair of exposed sensor cells is influenced by exposure to the radiation in response to the corresponding measured threshold voltage difference; and (4) determining a dosage of the radiation in response to the number of logical pairs of the exposed sensor cells determined to be influenced by exposure to the radiation. A non-radiation influenced threshold voltage shift may be measured and used in determining whether each logical pair of exposed sensor cells is influenced by radiation exposure.

Abstract: A method for radiation dosage measurement includes: (1) exposing a plurality of single-poly floating gate sensor cells to radiation; (2) measuring threshold voltage differences between logical pairs of the exposed sensor cells using differential read operations, wherein the sensor cells of each logical pair are separated by a distance large enough that radiation impinging on one of the sensor cells does not influence the other sensor cell; (3) determining whether each logical pair of exposed sensor cells is influenced by exposure to the radiation in response to the corresponding measured threshold voltage difference; and (4) determining a dosage of the radiation in response to the number of logical pairs of the exposed sensor cells determined to be influenced by exposure to the radiation. A non-radiation influenced threshold voltage shift may be measured and used in determining whether each logical pair of exposed sensor cells is influenced by radiation exposure.

Abstract: A method for radiation dosage measurement includes: (1) exposing a plurality of single-poly floating gate sensor cells to radiation; (2) measuring threshold voltage differences between logical pairs of the exposed sensor cells using differential read operations, wherein the sensor cells of each logical pair are separated by a distance large enough that radiation impinging on one of the sensor cells does not influence the other sensor cell; (3) determining whether each logical pair of exposed sensor cells is influenced by exposure to the radiation in response to the corresponding measured threshold voltage difference; and (4) determining a dosage of the radiation in response to the number of logical pairs of the exposed sensor cells determined to be influenced by exposure to the radiation. A non-radiation influenced threshold voltage shift may be measured and used in determining whether each logical pair of exposed sensor cells is influenced by radiation exposure.

Abstract: A method for radiation dosage measurement includes: (1) exposing a plurality of single-poly floating gate sensor cells to radiation; (2) measuring threshold voltage differences between logical pairs of the exposed sensor cells using differential read operations, wherein the sensor cells of each logical pair are separated by a distance large enough that radiation impinging on one of the sensor cells does not influence the other sensor cell; (3) determining whether each logical pair of exposed sensor cells is influenced by exposure to the radiation in response to the corresponding measured threshold voltage difference; and (4) determining a dosage of the radiation in response to the number of logical pairs of the exposed sensor cells determined to be influenced by exposure to the radiation. A non-radiation influenced threshold voltage shift may be measured and used in determining whether each logical pair of exposed sensor cells is influenced by radiation exposure.

Abstract: A two-terminal, single-poly floating gate memristor includes parallel-connected, asymmetrical readout and injection transistors having a shared floating gate structure, and a diode connected to drain terminals of the asymmetrical transistors. The injection transistor is configured with relatively high source/drain-to-gate capacitances to facilitate EEPROM-type (floating gate) program/erase operations (e.g., hot carrier injection and band-to-band tunneling of holes), and the readout transistor is configured (e.g., using a threshold voltage implant) to facilitate low-voltage readout operations. The diode is configured to function both as a limiting resistor that prevents over-erase during high-voltage erase operations, and also to prevent sneak (leakage) currents during low-voltage readout operations. The diode is implemented using either p-n junction or Schottky diode configurations formed on bulk silicon, or a lateral diode configurations disclosed for SOI substrates.

Abstract: A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell for use in a CMOS IC, where the CEONOS NVM cell requires two or three additional masks, but is otherwise substantially formed using the same standard CMOS flow processes used to form NMOS transistors. The cell is similar to an NMOS cell but includes an oxide-nitride-oxide (ONO) layer that replaces the standard NMOS gate oxide and serves to store NVM data. The cells utilize special source/drain engineering to include pocket implants and lightly-doped drain extensions, which facilitate program/erase of the CEONOS NVM cells using low voltages (e.g., 5V). The polysilicon gate, source/drain contacts and metallization are formed using corresponding NMOS processes. The CEONOS NVM cells are arranged in a space-efficient X-array pattern such that each group of four cells share a drain diffusion and three bit lines. Programming involves standard CHE injection or pulse agitated interface substrate hot electron injection (PAISHEI).

Abstract: Solid state radiation sensors include a floating gate (FG) structure having a large control capacitor region disposed on thick dielectric portion over a control gate (CG) implemented by an isolated P-well region, and a tunneling capacitor region disposed on thin gate oxide dielectric over another tunneling gate (TG) isolated P-well region. Opposite voltages (e.g., +5V/?5V) are respectively applied to the CG and TG P-well regions to charge the FG structure by Fowler-Nordheim tunneling. During exposure, radiation striking the sensor discharges the FG structure by generating electron-hole pairs in the dielectric portion separating the CG P-well region and the control capacitor region. After exposure, the total ionizing dose (TID) is calculated, e.g., by measuring the threshold voltage shift of a CMOS readout inverter controlled by the residual charge stored on the FG structure. Sensor performance is enhanced by metal plates, utilizing two control capacitors, or modifying the FG electrode layout.

Abstract: Photovoltaic devices are produced using a minimally modified standard process flow by forming lateral P-I-N light-sensitive diodes on silicon islands that are isolated laterally by trenches performed by RIE, and from an underlying support substrate by porous silicon regions. P+ and N+ doped regions are formed in a P? epitaxial layer, trenches are etched through the epitaxial layer into a P+ substrate, a protective layer (e.g., SiN) is formed on the trench walls, and then porous silicon is formed (e.g., using HF solution) in the trenches that grows laterally through the P+ substrate and merges under the island. The method is either utilized to form low-cost embedded photovoltaic arrays on CMOS IC devices, or the devices are separated from the P+ substrate by etching through the porous silicon to produce low-cost, high voltage solar arrays for solar energy sources, e.g., solar concentrators.

Abstract: A photovoltaic device includes lateral P-I-N light-sensitive diodes disposed on a silicon island formed by a P? epitaxial layer and surrounded by trenches that provide lateral isolation, where the island is separated from the substrate by a porous silicon region that is grown under the island and isolates the lower portions of the photovoltaic device from the highly doped substrate. The trenches extend through the P? epitaxial material into the P+ substrate to facilitate self-limiting porous silicon formation at the bottom of the island, and also to suppress electron-hole recombination. A protective layer (e.g., SiN) is formed on the trench walls to further restrict porous silicon formation to the bottom of the island. Black silicon on the trench walls enhances light capture. The photovoltaic devices form low-cost embedded photovoltaic arrays on CMOS IC devices, or are separated to produce low-cost, HV solar arrays for solar energy sources, e.g. for solar concentrators.

Abstract: A photovoltaic device includes lateral P-I-N light-sensitive diodes disposed on a silicon island formed by a P? epitaxial layer and surrounded by trenches that provide lateral isolation, where the island is separated from the substrate by a porous silicon region that is grown under the island and isolates the lower portions of the photovoltaic device from the highly doped substrate. The trenches extend through the P? epitaxial material into the P+ substrate to facilitate self-limiting porous silicon formation at the bottom of the island, and also to suppress electron-hole recombination. A protective layer (e.g., SiN) is formed on the trench walls to further restrict porous silicon formation to the bottom of the island. Black silicon on the trench walls enhances light capture. The photovoltaic devices form low-cost embedded photovoltaic arrays on CMOS IC devices, or are separated to produce low-cost, HV solar arrays for solar energy sources, e.g. for solar concentrators.

Abstract: Photovoltaic devices are produced using a minimally modified standard process flow by forming lateral P-I-N light-sensitive diodes on silicon islands that are isolated laterally by trenches performed by RIE, and from an underlying support substrate by porous silicon regions. P+ and N+ doped regions are formed in a P? epitaxial layer, trenches are etched through the epitaxial layer into a P+ substrate, a protective layer (e.g., SiN) is formed on the trench walls, and then porous silicon is formed (e.g., using HF solution) in the trenches that grows laterally through the P+ substrate and merges under the island. The method is either utilized to form low-cost embedded photovoltaic arrays on CMOS IC devices, or the devices are separated from the P+ substrate by etching through the porous silicon to produce low-cost, high voltage solar arrays for solar energy sources, e.g., solar concentrators.

Abstract: A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell for use in a CMOS IC, where the CEONOS NVM cell requires two or three additional masks, but is otherwise substantially formed using the same standard CMOS flow processes used to form NMOS transistors. The cell is similar to an NMOS cell but includes an oxide-nitride-oxide (ONO) layer that replaces the standard NMOS gate oxide and serves to store NVM data. The cells utilize special source/drain engineering to include pocket implants and lightly-doped drain extensions, which facilitate program/erase of the CEONOS NVM cells using low voltages (e.g., 5V). The polysilicon gate, source/drain contacts and metallization are formed using corresponding NMOS processes. The CEONOS NVM cells are arranged in a space-efficient X-array pattern such that each group of four cells share a drain diffusion and three bit lines. Programming involves standard CHE injection or pulse agitated interface substrate hot electron injection (PAISHEI).

Abstract: A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell production method for CMOS ICs, where the CEONOS NVM cell requires two or three additional masks, but can otherwise be formed using the same standard CMOS flow processes used to form NMOS transistors. A first additional mask is used to form an oxide-nitride-oxide (ONO) layer that replaces the standard NMOS gate oxide and serves to store NVM data (i.e., trapped charges). A second additional mask is used to perform drain engineering, including a special pocket implant and LDD extensions, which facilitates program/erase of the CEONOS NVM cells using low voltages (e.g., 5V). The polysilicon gate, source/drain contacts and metallization are formed using corresponding NMOS processes. The CEONOS NVM cells are arranged in a space-efficient X-array pattern such that each group of four cells share three bit lines. Programming involves standard CHE injection or pulse agitated interface substrate hot electron injection (PAISHEI).

Abstract: A non-volatile memory (NVM) cell and array includes a control capacitor, tunneling capacitor, CMOS inverter and output circuit. The CMOS inverter includes PMOS and NMOS inverter transistors. The control capacitor, tunneling capacitor and PMOS and NMOS inverter transistors share a common floating gate, which is programmed/erased by Fowler-Nordheim tunneling. The output circuit includes PMOS and NMOS select transistors. The PMOS inverter and select transistors share a common source/drain region. Similarly, the NMOS inverter and select transistors share a common source/drain region. This configuration minimizes the required layout area of the non-volatile memory cell and allows design of arrays with smaller footprints. Alternately, the tunneling capacitor may be excluded, further reducing the required layout area of the NVM cell.

Abstract: A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by either a standard CMOS process flow or a slightly modified CMOS process flow. The NVM cell includes read and injection transistors that share a common floating gate. The floating gate includes a portion disposed over the channel region of the read transistor, a portion disposed over the channel region of the injection transistor, and a portion extending into an enlarged drain diffusion area away from the channel regions, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitances. The source/drain of the injection transistor are formed using different LDD implants to achieve faster program/erase. Alternatively, an optional CHE enhancing implant is added to the source/drain of the injection transistor to enhance CHE programming. Both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension.

Abstract: A photovoltaic device includes lateral P-I-N light-sensitive diodes respectively formed in portions of a planar semiconductor material (e.g., polycrystalline or crystalline silicon) layer that is entirely disposed on an insulating material (e.g., SiO2) layer utilizing, e.g., STI or SOI techniques. Each light-sensitive diode includes parallel elongated doped regions respectively formed by P+ and N+ dopant extending entirely through the semiconductor layer material and separated by an intervening elongated intrinsic (native) region. The light-sensitive diodes are connected in series by patterned conductive (e.g., metal film) structures. Optional bypass diodes are formed next to each lateral P-I-N light-sensitive diodes. Optional trenches are defined between adjacent light-sensitive diodes.

Abstract: A photovoltaic device includes lateral P-I-N light-sensitive diodes respectively formed in portions of a planar semiconductor material (e.g., polycrystalline or crystalline silicon) layer that is entirely disposed on an insulating material (e.g., SiO2) layer utilizing, e.g., STI or SOI techniques. Each light-sensitive diode includes parallel elongated doped regions respectively formed by P+ and N+ dopant extending entirely through the semiconductor layer material and separated by an intervening elongated intrinsic (native) region. The light-sensitive diodes are connected in series by patterned conductive (e.g., metal film) structures. Optional bypass diodes are formed next to each lateral P-I-N light-sensitive diodes. Optional trenches are defined between adjacent light-sensitive diodes.

Abstract: A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by either a standard CMOS process flow or a slightly modified CMOS process flow. The NVM cell includes read and injection transistors that share a common floating gate. The floating gate includes a portion disposed over the channel region of the read transistor, a portion disposed over the channel region of the injection transistor, and a portion extending into an enlarged drain diffusion area away from the channel regions, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitances. The source/drain of the injection transistor are formed using different LDD implants to achieve faster program/erase. Alternatively, an optional CHE enhancing implant is added to the source/drain of the injection transistor to enhance CHE programming. Both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension.

Abstract: An asymmetric non-volatile memory (NVM) cell for a CMOS IC formed by a standard CMOS process flow used to form both low voltage and high voltage transistors on a substrate. The NVM cell includes an NMOS floating gate transistor and an optional select transistor. The floating gate transistor includes an elongated floating gate having a first portion disposed over the channel region C150, a second portion extending into an enlarged drain diffusion area D150 away from the channel region, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitance. The width of the floating gate extension portion is minimized, while both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension. HV LDD implant in the NVM transistor is replaced by LV LDD. The floating gate is formed using substantially U-shaped or J-shaped polysilicon structures. Various array addressing schemes are disclosed.