METHOD FOR PRODUCING PHOTOVOLTAIC DEVICE ISOLATED BY POROUS SILICON
Photovoltaic devices are produced using a minimally modified standard process flow by forming lateral P-I-N light-sensitive diodes on silicon islands that are isolated laterally by trenches performed by RIE, and from an underlying support substrate by porous silicon regions. P+ and N+ doped regions are formed in a P− epitaxial layer, trenches are etched through the epitaxial layer into a P+ substrate, a protective layer (e.g., SiN) is formed on the trench walls, and then porous silicon is formed (e.g., using HF solution) in the trenches that grows laterally through the P+ substrate and merges under the island. The method is either utilized to form low-cost embedded photovoltaic arrays on CMOS IC devices, or the devices are separated from the P+ substrate by etching through the porous silicon to produce low-cost, high voltage solar arrays for solar energy sources, e.g., solar concentrators.
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This invention relates to photovoltaic devices, and particularly to photovoltaic devices including P-I-N light sensitive diodes.BACKGROUND OF THE INVENTION
High voltage low-power photovoltaic sources have a variety of applications including solar chargers, wireless sensors and detectors, different portable consumer products, self-powered light detectors, energy sources for driving MEMS engines, etc. Many of the state of the art integrated circuits (ICs) are capable of operating at milliwatt-microwatt power consumption levels that can be obtained from photovoltaic cells fabricated on the same silicon chip as the IC. Such photovoltaic HV sources can also be used for continuous charging of batteries in power management systems to prevent total discharge and enabling energy savings. If the output of the photoelectric source is high enough, it can be connected to a battery or energy storage capacitor (supercapacitor) to allow higher current peak values. The resulting energy harvesting system strongly increases the application field covering long-range RFID systems, smart dust products, etc.
There are two conventional approaches in integrating photovoltaic sources into the silicon IC.
The first conventional approach is to use conventional low-voltage (single p-n junction) photovoltaic elements and dc-dc boost converters capable of increasing the low-level input voltages to the levels of the IC system voltage (Vdd). This approach is utilized, for example, in products such as LTC 3108 produced by Linear Technology Corporation of Milpitas, Calif., USA. This approach requires a complicated analog circuit, and faces many challenges related to the need to process very low signals and distinguish them from stray voltages.
The second conventional approach is to connect the individual solar cells (p-n junction) in series on silicon (not the external connection of silicon dice). Some companies (e.g., Clare, an IXYS Company, of Beverly, Mass., USA) fabricate specialized chips that generate voltages up to several volts by connecting individual solar cells on the chip (e.g., Clare's CPC1822-CPC1832 products).
In most cases, in order to obtain high voltages, solar cells are fabricated at the isolated areas of silicon and then connected in series or series-and-parallel combinations.
A standard photovoltaic p-n diode cell typically generates from 0.4 to 0.7 V under illumination by the sunlight. The connection of photovoltaic elements can be, of course, external, if the solar cells are on separate silicon substrates (separate wafers). This is what can be found in most commercial solar energetics (photovoltaic) systems. It is clear that external connections strongly increase the system cost and decrease reliability. In case of working with light concentrators, the problem of connections becomes a bottleneck since the currents from individual solar wafers reach tens and hundreds of Amperes. HV cells solve the problem by decreasing the current for the same light power per unit square of the solar array surface.
Several solutions have been proposed to make HV solar cells on one silicon substrate.
A high voltage multi-junction solar cell is disclosed in U.S. Pat. No. 4,341,918 (Evans, et. al), where a plurality of discrete voltage generating regions or unit cells are formed in a single generally planar semiconductor body. The unit cells comprise doped regions of opposite conductivity type separated by a gap or undiffused region. Metal contacts connect adjacent cells together in series so that the output voltages of the individual cells are additive. A problem with this approach is that special metallization is needed by forming a pattern of parallel bars of aluminum paste that is screen-printed on the surface and fired to assure penetration of the aluminum through the diffused N+ region on this face and to make connection to P+ regions. Another problem is that the output voltage is limited since the common P-type base shunts the serially connected individual N+P (base) junctions.
Attempts to isolate the elements comprising the high-voltage where SOI isolation was employed are disclosed, for example, in U.S. Pat. No. 6,281,428 (Chiu et al). Chiu has demonstrated how to use the oxide layer of the SOI wafer as the isolating layer. The approach makes use of serially connected transverse photovoltaic cells formed by diffusions using special masks (six masks together with a special mask forming a mesa structure on the peripheral region to isolate the light-sensitive array). The photosensitive diodes are connected in series by metal plugs. Light enters the photosensitive array through dielectric layers.
The limitation of the approach taught by Chiu is the large number of additional masks specially added to the SOI core process in case of thin silicon on insulator layers. Also, for the mentioned thick Si substrates it is difficult to reach the bottom oxide-BOX (32) interface with the P+ diffusion, making the proposed P+-p device structure problematic.
What is needed is a photovoltaic device that addresses the problems listed above and can be produced using a standard process flow with minimal additional masks.SUMMARY OF THE INVENTION
The present invention is directed to a method for fabricating a photovoltaic device on an “island” portion of a silicon epitaxial layer that is disposed on a monocrystalline silicon substrate that involves forming porous silicon between the “island” and the underlying silicon substrate, whereby the porous silicon isolates the photovoltaic device from the underlying substrate. The epitaxial layer includes a base (lower) epitaxial portion (i.e., a portion disposed adjacent to epi/substrate silicon substrate, and which due to intentional tuning the epi process or up-diffusion of dopant from the substrate, has an intermediate (first) doping level that is greater than the relatively low (second) doping level of an upper portion of the epitaxial layer, and is lower than a relatively high (third) doping level of the silicon substrate. The method includes forming P+ and N+ doped regions in the upper epitaxial layer (which later serve to form lateral P-I-N light-sensitive diodes), then forming trenches extending through the epitaxial layer into the silicon substrate that form side edges of the island, and then utilizing an etchant entered into the trench to form a porous silicon region that extends under the island and electrically isolates the island from the silicon substrate. A benefit of the disclosed production method is that, by initiating the porous silicon formation at the bottom of the trench, the porous silicon grows in the silicon substrate and extends under the island. Further, the change from high doping level to low doping level in the base epitaxial portion serves both as an enabler of a self-limiting mechanism that stops the upward growth of porous silicon in the island, and also serves to suppress electron-hole recombination. Moreover, the production method is easily integrated into standard process flows (e.g., established CMOS, PM CMOS, or MEMS process flows) with only the addition of one mask used to form the trenches, whereby the photovoltaic device can be embedded into (i.e., formed on the same base substrate as) an integrated circuit device, wherein the photovoltaic device is electrically isolated from the base substrate by the trenches and porous silicon. By forming the light-sensitive diodes using existing (or only slightly modified) process flows, the present invention enables low-cost embedded photovoltaic arrays that can be integrally formed as part of a CMOS IC (electronic) device (e.g., PM, MEMS, RFID and other mixed signal/RFCMOS devices). Alternatively, the disclosed photovoltaic device can be separated by etching through the porous silicon to provide, for example, low-cost, high voltage solar arrays for solar energy concentrators.
According to an aspect of the present invention, various existing processes are beneficially utilized to produce isolated photovoltaic devices in a highly efficient and cost effective manner. For example, the trenches are formed by reactive ion etching through said epitaxial layer into said silicon substrate, which produces side walls that efficiently capture and retain light. Optional black silicon is formed on the trench walls to further enhance light capture. The porous silicon is efficiently generated using various established methods, such as an electochemical etch (e.g., using an HF solution and applied current) or galvanic etching, and passivation is then performed (e.g., by oxidation or deposition of ALD alumina) to decrease surface recombination. A protective layer (e.g., SiN formed by CVD) is selectively formed on the trench walls and over the island to prevent damage during processing, and a portion of the protective layer is removed (e.g., by REI) from the bottom of the trenches to facilitate porous silicon formation in substrate regions under the island. After porous silicon formation is completed, and optional porous silicon oxidation performed, the trench is filled with a dielectric and the protective layer is removed from the upper surface of the island, thereby exposing the P+ and N+ doped regions during subsequent contact formation using existing electrical conductor formation processes.
These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings, where:
The present invention relates to an improvement in photovoltaic devices produced substantially entirely using existing process flows. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. As used herein, directional terms such as “upper”, “lower”, “above”, “below”, “vertical” and “horizontal” are intended to provide relative positions for purposes of description, and are not intended to designate an absolute frame of reference. The terms “coupled” and “connected”, which are utilized herein, are defined as follows. The term “connected” is used to describe a direct connection between two circuit elements, for example, by way of a metal line formed in accordance with normal integrated circuit fabrication techniques. In contrast, the term “coupled” is used to describe either a direct connection or an indirect connection between two circuit elements. For example, two coupled elements may be directly connected by way of a metal line, or indirectly connected by way of an intervening circuit element (e.g., a capacitor, resistor, inductor, or by way of the source/drain terminals of a transistor). Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
The periphery of island 110 is defined by trench regions (trenches) T1 and T2, whereby island 110 is electrically isolated in a lateral direction from a remainder of substrate 101 by trenches T1 and T2, which are typically filled with a passivation material (not shown). As such, island 110 is defined by a width IW measured between a first vertical side wall 114-1 and a second vertical side wall 114-2, and an orthogonally oriented length IL. Trenches T1 and T2, which are formed in the manner described below, respectively have widths TW extending between side walls 114-1 and 114-2 of island 110 and facing side walls 104-1 and 104-2 of adjacent portions of epitaxial layer 103, and have depths TD extending from upper surface 116 of upper epitaxial portion 113 to bottom surfaces 104-31 and 104-32. Note that the features depicted in
Referring to the top of island 110, photo-voltaic device 100 includes at least one lateral P-I-N photo-sensitive diode 120 formed by spaced-apart P+ and N+ doped regions 124 and 125. Although photo-voltaic device 100 typically includes multiple lateral light-sensitive P-I-N diodes, only one such diode 120 is shown in
According to an aspect of the present invention, base epitaxial portion 111 of island 110 is entirely disposed on a porous silicon region 115 that serves, for example, to electrically isolate island 110 from underlying structures (i.e., in the vertical direction), such as substrate 101. As indicated by the shaded region below island 110, porous silicon region 115 extends under the entire width IW and the entire length IL of island 110, and also extends into portions of substrate 101 disposed adjacent to trenches T1 and T2. As understood in the art, the phrase “porous silicon” refers to a form of silicon including nanopores and mesopores (voids) having a width in the range of 2 to 10 nm and 10 to 100 nm respectively (typically, the size of the pores is in the range of 20-50 nm). The term “porosity” is generally used to define the amount of space occupied by pores (voids) in a porous silicon structure, which can range from 4% to 95%. As used herein, the phrases “porous silicon” (PS) and “oxidized porous silicon” (OPS) refer to regions of silicon material (i.e., monocrystalline silicon, polycrystalline silicon or silicon germanium) that are processed to include dispersed nanopores such that the silicon material exhibits an electrical resistance greater than 107 Ohm. Note that OPS is formed by oxidizing PS (either chemically or electro-chemically or thermally or by any other means) to increase its electrical resistance. For brevity, the phrase “porous silicon” is used herein to refer to both PS and OPS.
According to an embodiment of the present invention, base epitaxial portion 111 has an intermediate (first) P-type doping concentration forming P+/− (first) doping level (e.g., producing conductivity in the range of 0.1-0.2 ohm-cm), upper epitaxial portion 113 and has a relatively low (second) P-type doping concentration forming a P− (second) doping level (e.g., producing conductivity in the range of 1-10 ohm-cm), and P+ substrate 101 has a relatively high (third) P-type doping concentration forming a P+ (third) doping level (e.g., producing conductivity in the range of 0.01-0.02 ohm-cm). The significance of the difference between these doping levels is that, as described in additional detail below, this difference causes the etching process used to form porous silicon region 115 to be self-limiting (i.e., stop) in the direction of P− epitaxial portion 113 when the etch front approaches the P−/P+ interface 112 between P+/− base epitaxial portion 111 and P− upper epitaxial portion 113, resulting in a high level of control over the thickness of porous silicon region 115 and good lateral uniformity. That is, porous silicon region 115 typically extends into portions of base epitaxial portion 111, but stops before it reaches lightly doped P− upper epitaxial region 113.
According to the embodiment depicted in
The EC process etch rate (PS formation) strongly depends on the doping of the P+ substrate. During experiments conducted by the inventors, samples were placed into a standard electrochemical cell that operated in the “galvanostatic” mode (i.e., under a constant current). The process lasted for typical times of about 50-100 seconds. The results of these experiments showed PS having been selectively created at the bottom of the trenches where the EC solution is in contact with the heavily doped Si substrate.
In another embodiment the surface of trenches was converted into PS by a special etch before SiN deposition and passivated by oxidation or deposition of ALD (atomic layer deposited) alumina (see, e.g., Extremely low surface recombination velocities in black silicon passivated by atomic layer deposition, Martin Otto, Matthias Kroll, Thomas Käsebier, Roland Salzer, Andreas Tünnermann et al., Applied Physics Letters, 100, 191603 (2012)). The formation of black silicon is believed to enhance light absorption inside the islands, providing a further advantage to photovoltaic devices formed in accordance with the present invention. In addition, as indicated in
According to an alternative embodiment, the EC etching process is modified to generate electrochemical oxidation in order to increase the resistivity of the PS region. Forming porous silicon without special further oxidation facilitates effective electrical isolation that is sufficient for operating solar cell arrays (i.e., 107-108 Ohm for an isolated 100 μm long and 12 μm wide silicon island with respect to the P+ substrate). During practical testing, subsequent mild electrochemical oxidation increased the resistance of the PS to 1010-1011 Ohm.
According to another alternative embodiment, in addition to the EC process described above, similar PS formation is achieved with Galvanic Etching, where electrochemical closed circuit is also formed but no external bias applied. The galvanic etching (GE) to produce PS layers is based on the chemical oxidation-reduction reaction at the interface of the metallic back contact and using of the HF-oxidant (H2O2) solution. The reaction proceeds via generation of a hole at the metal-covered (Au or silver alloy) side after oxidation of the metal while the just generated hole diffuses to the other side of the silicon wafer to react with HF and start the silicon etching process. An advantage of the GE method is its parallel processing nature, enabling the production of many samples simultaneously. A demonstration of the GE process is shown in
Photovoltaic device 100B also differs from device 100 (
Array 100C provides an advantage over conventional photovoltaic devices in that the associated fabrication processes needed to produce the various photovoltaic device structures of array 100C can be easily integrated into standard process flows (e.g., established CMOS process flows, power management (PV) CMOS process flows, and microelectromechanical system (MEMS) process flows) without requiring any (or requiring very few) additional masks. Thus, the novel structural arrangement of array 100C is easily integrated into standard process flows using only slightly modified) process steps. By forming photovoltaic devices using existing (or only slightly modified) process flows, the present invention facilitates the use of photovoltaic device 100C to form low-cost embedded photoelectric arrays on IC devices formed by these standard process technologies. For example, referring briefly to FIG. 6, a simplified CMOS IC 300 is shown that includes both photovoltaic device 100C (described above) and a generic CMOS circuit 310 (e.g., a PM, MEMS, RFID or other mixed signal/RFCMOS device) that are entirely formed on a monocrystalline silicon substrate 301 using a standard CMOS process flow that is modified as described above to facilitate trench and PS formation. In this example, photovoltaic device 100C is connected as a supply power to CMOS circuit 310 by way of metal lines formed in accordance with the techniques described herein.
According to another alternative embodiment of the present invention described with reference to
Although the present invention has been described with respect to certain specific embodiments, it will be clear to those skilled in the art that the inventive features of the present invention are applicable to other embodiments as well, all of which are intended to fall within the scope of the present invention. For example, although the process is described above with reference to the formation of photovoltaic devices on a P-type substrate, the methods descried above may be modified using techniques known in the art to produce similar devices on N-type substrates. Further, the Si epitaxial layer described above may be implemented using another semiconductor such as Ge, SiGe and GaN.
1. A method for fabricating a photovoltaic device on an epitaxial layer disposed on a silicon substrate, wherein a base epitaxial portion of the epitaxial layer adjacent to the silicon substrate has a first doping level that is greater than a second doping level of an upper epitaxial portion of the epitaxial layer, and is lower than a third doping level of the silicon substrate, the method comprising:
- forming a plurality of doped regions in the epitaxial layer including at least one P+ doped region and at least one N+ doped region;
- forming first and second elongated trenches extending through the epitaxial layer into the silicon substrate such that an elongated island is formed by a portion of said epitaxial layer that is disposed between first and side walls defined by said first and second elongated trenches, wherein at least one P+ doped region and the at least one N+ doped region are disposed on said elongated island; and
- forming a porous silicon region under said elongated island such that said porous silicon region electrically isolates said elongated island from said silicon substrate.
2. The method of claim 1, wherein forming said elongated trenches comprises reactive ion etching through said epitaxial layer into said silicon substrate.
3. The method of claim 2, further comprising forming black silicon on side walls of the island.
4. The method of claim 1, wherein forming said porous silicon region comprises performing an electochemical etch through bottom surfaces of the first and second trenches such that the electochemical etch generates porous silicon portions that merge under the elongated island.
5. The method of claim 1 where the drive in of N+ and P+ implant is performed after the trench etch with a target to reach the surface of the formed porous silicon.
6. The method of claim 4, wherein performing said electochemical etch comprises placing said substrate in a hydro-fluoric (HF) solution.
7. The method of claim 6, wherein performing said electochemical etch further comprises generating a current between an electrode disposed on a lower surface of the substrate and the hydrofluoric (HF) solution.
8. The method of claim 5, further comprising forming a protective layer on said first and second side walls of the island after performing said electochemical etch.
9. The method of claim 8, wherein forming the protective layer comprises depositing Silicon Nitride on the first and second side walls and on said bottom surfaces of the first and second trenches.
10. The method of claim 9, wherein disposing Silicon Nitride on the first and second side walls and on said bottom surfaces comprises performing chemical vapor deposition (CVD).
11. The method of claim 8, further comprising removing a portion of said protective layer disposed on said bottom surfaces of said trench before performing said electochemical etch.
12. The method of claim 11, wherein removing said portion of said protective layer comprises removing said portion by reactive ion etching.
13. The method of claim 12, wherein performing said electochemical etch further comprises generating a current between an electrode disposed on a lower surface of the substrate and the hydro-fluoric (HF) solution.
14. The method of claim 1, further comprising forming electrical contacts on the epitaxial portion such that each electrical contact forms an electrical connection between a first N+ doped region associated with a first diode and a P+ doped region of an adjacent second diode.
15. The method of claim 1, wherein forming said porous silicon region comprises performing a galvanic etch through bottom surfaces of the first and second trenches such that the galvanic etch generates porous silicon regions that merge under the elongated island.
16. The method of claim 1, further comprising etching said porous silicon layer such that said island becomes detached from said silicon substrate.
17. The method of claim 16, further comprising:
- forming a second epitaxial layer on said substrate;
- forming a second plurality of doped regions in the second epitaxial layer;
- forming third and fourth elongated trenches extending through the second epitaxial layer into the silicon substrate; and
- forming a second porous silicon region in said silicon substrate.
18. A method for fabricating an embedded high voltage (HV) photovoltaic device on an epitaxial layer disposed on a silicon substrate, wherein a doping level of the epitaxial layer is lower than a doping level of the silicon substrate, the method comprising:
- forming a plurality of spaced apart doped regions on the epitaxial layer;
- forming a plurality of trenches extending through the epitaxial layer into the silicon substrate such that a plurality of islands are formed by portions of said epitaxial layer disposed between each adjacent pair of said plurality of trenches, wherein at least one pair of said doped regions is disposed on each of the plurality of islands;
- forming a porous silicon region under each of said plurality of said islands by exposing silicon inside the trenches to an etchant such that said porous silicon region electrically isolates all of said islands from said silicon substrate; and
- forming electrical conductors on the top of epitaxial layer portions that operably connect said plurality of doped regions to form a plurality of series-connected photo sensitive diodes.
19. A method for isolating an embedded photovoltaic device formed on a silicon substrate having a high doping level and including an epitaxial layer having a low doping level, the method comprising:
- forming first and second trenches extending through the epitaxial layer into the silicon substrate such that an island is formed by a portion of the epitaxial layer portion that is disposed between the first and second trenches; and
- forming a porous silicon region under said island by applying an etchant to bottom surfaces of said first and second trenches such that said porous silicon region extends entirely under and electrically isolates said island from said silicon substrate,
- wherein said embedded photovoltaic device is at least partially disposed on said epitaxial layer portion forming said island.
Filed: Mar 14, 2013
Publication Date: Sep 18, 2014
Applicants: Yissum Research Development Company of the Hebrew University of Jerusalem Ltd. (Jerusalem), Tower Semiconductor Ltd. (Migdal Haemek)
Inventors: Yakov Roizin (Afula), Evgeny Pikhay (Haifa), Irit Chen-Zamero (Haifa), Ora Eli (Afula), Micha Asscher (Jerusalem), Amir Saar (Jerusalem)
Application Number: 13/831,473
International Classification: H01L 31/042 (20060101);